Showing papers on "Wafer published in 2003"

Low-temperature wafer-scale production of ZnO nanowire arrays.

Abstract: Since the first report of ultraviolet lasing from ZnO nanowires, substantial effort has been devoted to the development of synthetic methodologies for one-dimensional ZnO nanostructures. Among the various techniques described in the literature, evaporation and condensation processes are favored for their simplicity and high-quality products, but these gas-phase approaches generally require economically prohibitive temperatures of 800–900 8C. Despite recent MOCVD schemes that reduced the deposition temperature to 450 8C by using organometallic zinc precursors, the commercial potential of gas-phase-grown ZnO nanowires remains constrained by the expensive and/or insulating (for example, Al2O3) substrates required for oriented growth, as well as the size and cost of the vapor deposition systems. A low-temperature, large-scale, and versatile synthetic process is needed before ZnO nanowire arrays find realistic applications in solar energy conversion, light emission, and other promising areas. Solution approaches to ZnO nanowires are appealing because of their low growth temperatures and good potential for scale-up. In this regard, Vayssieres et al. developed a hydrothermal process for producing arrays of ZnO microrods and nanorods on conducting glass substrates at 95 8C. Recently, a seeded growth process was used to make helical ZnO rods and columns at a similar temperature. Here we expand on these synthetic methods to produce homogeneous and dense arrays of ZnO nanowires that can be grown on arbitrary substrates under mild aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two-inch plastic substrates, which demonstrate the ease of commercial scale-up. The simple two-step procedure yields oriented nanowire films with the largest surface area yet reported for nanowire arrays. The growth process ensures that a majority of the nanowires in the array are in direct contact with the substrate and provide a continuous pathway for carrier transport, an important feature for future electronic devices based on these materials. Well-aligned ZnO nanowire arrays were grown using a simple two-step process. In the first step, ZnO nanocrystals (5–10 nm in diameter) were spin-cast several times onto a four-inch Si(100) wafer to form a 50–200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 150 8C to ensure particle adhesion to the wafer surface. The ZnO nanocrystals were prepared according to the method of Pacholski. A NaOH solution in methanol (0.03m) was added slowly to a solution of zinc acetate dihydrate (0.01m) in methanol at 60 8C and stirred for two hours. The resulting nanoparticles are spherical and stable for at least two weeks in solution. After uniformly coating the silicon wafer with ZnO nanocrystals, hydrothermal ZnO growth was carried out by suspending the wafer upside-down in an open crystallizing dish filled with an aqueous solution of zinc nitrate hydrate (0.025m) and methenamine or diethylenetriamine (0.025m) at 90 8C. Reaction times spanned from 0.5 to 6 h. The wafer was then removed from solution, rinsed with deionized water, and dried. A field-emission scanning electron microscope (FESEM) was used to examine the morphology of the nanowire array across the entire wafer, while single nanowires were characterized by transmission electron microscopy (TEM). Nanowire crystallinity and growth direction were analyzed by X-ray diffraction and electron diffraction techniques. SEM images taken of several four-inch samples showed that the entire wafer was coated with a highly uniform and densely packed array of ZnO nanowires (Figure 1). X-ray diffraction (not shown) gave a wurtzite ZnO pattern with an enhanced (002) peak resulting from the vertical orientation of the nanowires. A typical synthesis (1.5 h) yielded wires with diameters ranging between 40–80 nm and lengths of 1.5–2 mm.

Laser beam machining method

Abstract: The invention provides a laser beam machining method characterized by comprising the steps of mounting a protective tape (25) on the surface (3) of a wafer (1a), radiating laser light (L) by using the back (21) of a wafer (1a) as a laser light incidence plane with an optical converging point (P) positioned in a substrate (15) to thereby form a melt processing region (13) for melt processing by multiphoton absorption, forming, by means of the melt processing region (13), a cutting start region (8) on the side within a predetermined distance from the laser light incidence plane along a predetermined cutting line (5) on the wafer (1a), mounting an expand tape (23) on the back (21) of the wafer (1a), and stretching the expand tape (23) to thereby separate a plurality of chip-like portions (24) from each other that are formed by the wafer (1a) being cut with the cutting start region (8) used as the starting point.

Multi-dice chip scale semiconductor components and wafer level methods of fabrication

Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Semiconductor device and method of fabricating the same

Abstract: A semiconductor device improves the electron mobility in the n-channel MOSFET and reduces the bend or warp of the semiconductor substrate or wafer. The first nitride layer having a tensile stress is formed on the substrate to cover the n-channel MOSFET. The tensile stress of the first nitride layer serves to relax a compressive stress existing in the channel region. The second nitride layer having an actual compressive stress is formed on the substrate to cover the p-channel MOSFET. The first and second nitride layers serve to decrease bend or warp of the substrate. Preferably, the first nitride layer is a nitride layer of Si formed by a LPCVD process, and the second nitride layer is a nitride layer of Si formed by a PECVD process.

Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology

Abstract: Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating large CMUTs, offers advantages over the traditionally micromachined CMUTs. First, forming a vacuum-sealed cavity is relatively easy since the wafer bonding is performed in a vacuum chamber. Second, this process enables better control over the gap height, making it possible to fabricate very small gaps (less than 0.1 /spl mu/m). Third, since the membrane is made of single crystal silicon, it is possible to predict and control the mechanical properties of the membrane to within 5%. Finally, the number of process steps involved in making a CMUT has been reduced from 22 to 15, shortening the device turn-around time. All of these advantages provide repeatable fabrication of CMUTs featuring predictable center frequency, bandwidth, and collapse voltage.

Fabrication of Complex Three-Dimensional Microchannel Systems in PDMS

Abstract: This paper describes a method for fabricating three-dimensional (3D) microfluidic channel systems in poly(dimethylsiloxane) (PDMS) with complex topologies and geometries that include a knot, a spiral channel, a “basketweave” of channels, a chaotic advective mixer, a system with “braided” channels, and a 3D grid of channels. Pseudo-3D channels, which are topologically equivalent to planar channels, are generated by bending corresponding planar channels in PDMS out of the plane into 3D shapes. True 3D channel systems are formed on the basis of the strategy of decomposing these complex networks into substructures that are planar or pseudo-3D. A methodology is developed that connects these planar and/or pseudo-3D structures to generate PDMS channel systems with the original 3D geometry. This technique of joining separate channel structures can also be used to create channel systems in PDMS over large areas by connecting features on different substrates. The channels can be used as templates to form 3D structu...

Heterogeneously integrated microsystem-on-a-chip

Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Processing apparatus with a chamber having therein a high-corrosion-resistant sprayed film

Abstract: A processing apparatus of the present invention has a mounted chamber holding a semiconductor wafer and having members for work-processing the substrate under any of heating, plasma and process gas or a combination of them, in which a film of Al 2 O 3 and Y 2 O 3 is formed on an inner wall surface of the chamber and on those exposed surface of the members within the chamber and has a high-corrosion resistance and insulating property and, when the process gas is introduced onto a processing surface of a semiconductor wafer and diffused into it, any product is less liable to be deposited on a plasma generation area and on those members held within the chamber.

Metal contact structure for solar cell and method of manufacture

Abstract: In a solar cell having p doped regions and n doped regions alternately formed in a surface of a semiconductor wafer in offset levels through use of masking and etching techniques, metal contacts are made to the p regions and n regions by first forming a base layer contacting the p doped regions and n doped regions which functions as an antireflection layer, and then forming a barrier layer, such as titanium tungsten or chromium, and a conductive layer such as copper over the barrier layer. Preferably the conductive layer is a plating layer and the thickness thereof can be increased by plating.

Production apparatus for manufacturing semiconductor device

Abstract: The present invention discloses a production apparatus for manufacturing semiconductor device which comprises a vacuum processing chamber where film formation or etching is performed for a semiconductor wafer, a gas introducing part for introducing a process gas into the vacuum processing chamber, and a shower head for uniformly diffusing the introduced process gas, where a plate having a plurality of gas blowing holes for blowing the process gas on the semiconductor wafer are arranged and opened with uniform density is provided on the face of a shower head opposing the semiconductor wafer. Each of the gas blowing holes opened in the plate is a steeped hole having a large diameter hole part and a small diameter hole part, formed by varying the step location in response to the pressure distribution of the process gas within the shower head so as to make the amount of the gas blown from respective gas blowing holes uniform.

Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon

Abstract: Charge-coupled devices (CCDs) have been fabricated on high-resistivity, n-type silicon. The resistivity, on the order of 10 000 /spl Omega//spl middot/cm, allows for depletion depths of several hundred micrometers. Fully depleted, back-illuminated operation is achieved by the application of a bias voltage to an ohmic contact on the wafer back side consisting of a thin in situ doped polycrystalline silicon layer capped by indium tin oxide and silicon dioxide. This thin contact allows for a good short-wavelength response, while the relatively large depleted thickness results in a good near-infrared response.

Fin fet devices from bulk semiconductor and method for forming

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

Preparation of Freestanding GaN Wafers by Hydride Vapor Phase Epitaxy with Void-Assisted Separation

Abstract: We have developed a novel technique for preparing large-scale freestanding GaN wafers. Hydride vapor phase epitaxy (HVPE) growth of thick GaN layer was performed on a GaN template with a thin TiN film on the top. After the cooling process of the HVPE growth, the thick GaN layer was easily separated from the template by the assistance of many voids generated around the TiN film. As a result, a freestanding GaN wafer was obtained. The wafer obtained had a diameter of 45 mm, and a mirror-like surface. The-full-width-at-half-maximum (FWHM) of (0002) and (1010) peaks in the X-ray rocking curve profile were 60 and 92 arcsec, respectively. The dislocation density was evaluated at 5×106 cm-3 by etch pit density measurement.

High rate deposition at low pressures in a small batch reactor

Abstract: A chemical vapor deposition reactor (59) including a wafer (60) boat (77) with a vertical stack of horizontally oriented susceptors (62) serving as thermal plates (76) and each having pins (228) extending upward for suspending a wafer (60) between a pair of susceptors (62). Reactant gas injector (65) and exhaust apparatus (272) are positioned to concentrate a forceful supply of reactant gas across each wafer (60) at a speed in excess of 10 cm/sec. The pressure is held in the range of 0.1 to 5,000 mTorr. The forceful gas flow avoids gas depletion effects, thinning the boundary layer and resulting in faster delivery of reactants to substrate surfaces, resulting in surface rate reaction limited operation. A plurality of individually controllable heaters (78) are spaced vertically around the sides of the boat (77). Temperature sensors (130) monitor the temperature along the boat (77) height and provide input to a controller (118) for adjusting the heater drive to optimize the temperature uniformity.

Side-opened out-of-plane microneedles for microfluidic transdermal liquid transfer

Abstract: We present the first hollow out-of-wafer-plane silicon microneedles having openings in the shaft rather than having an orifice at the tip. These structures are well suited for transdermal microfluidic applications, e.g., drug or vaccine delivery. The developed deep-reactive ion etching (DRIE) process allows fabrication of two dimensional, mechanically highly resistant needle arrays offering low resistance to liquid flows and a large exposure area between the fluid and the tissue. The presented process does not require much wafer handling and only two photolithography steps are required. Using a 3/spl times/3 mm/sup 2/ chip in a typical application, e.g., vaccine delivery, a 100 /spl mu/l volume of aqueous fluid injected in 2 s would cause a pressure drop of less than 2 kPa. The presented needles are approximately 210 /spl mu/m long.

A novel microelectronic gas sensor utilizing carbon nanotubes for hydrogen gas detection

Abstract: A novel microelectronic gas sensor utilizing carbon nanotubes (CNTs) in a thin-layered Pd/CNTs/n+-Si structure for hydrogen detection has been achieved. The sensor is fabricated on an n-type silicon wafer, which is needed as an ohmic supporting substrate. Multiwalled CNTs were grown selectively on the substrate via catalytic activation with microwave plasma enhanced chemical vapor deposition. The I–V characteristics of the sensor exhibit Schottky diode behavior at room temperature with marked sensitivity or current changes in the presence of hydrogen. Increasing detection sensitivity in hydrogen sensing was observed with increasing operating temperature. The results demonstrate that CNTs configured as a gas sensor has high sensitivity to hydrogen over a wide temperature range. Behaviors of the sensor in the presence of hydrogen and at elevated temperature were discussed. The successful utilization of CNTs in gas sensors may open a new door for the development of novel nanostructure gas-sensing devices.

Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs

Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.

Method for fabrication of semiconductor device

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Wafer bonding of thinned electronic materials and circuits to high performance substrates

Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

ALD apparatus and ALD method for manufacturing semiconductor device

Abstract: Disclosed are PEALD (plasma-enhanced atomic layer deposition) apparatus and PEALD method for manufacturing a semiconductor device, the PEALD apparatus comprising: a housing including a reaction chamber in which a deposition reaction is performed; a rotary disk unit installed in the housing and provided with a plurality of susceptors for receiving wafers thereon so as to move the wafers; a gas spray unit mounted on the upper end of the housing above the rotary disk unit, and provided with first reactive gas sprayers, second reactive gas sprayers and inert gas sprayers on a lower surface of a circular disk for spraying respective gases into the housing; a gas feed unit connected to the gas spray unit for supplying first and second reactive gases and a purge gas into the housing; a gas exhaust port formed around the rotary disk unit; and a plasma generator for generating plasma to excite the second reactive gas.

Wafer-level package for micro-electro-mechanical systems

Abstract: A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing a metal layer on one of a first wafer and a second wafer; bonding the first wafer and the second wafer using the metal layer deposited on one of the first wafer and the second wafer; forming a through-wafer via in one of the first wafer and the second wafer; filling the through-wafer via with a conductive material; and forming a cavity in the one of the first wafer and the second wafer having the through-wafer via, wherein the cavity is superposable over a device.

Single wafer encapsulation of MEMS devices

Abstract: Packaging of micro-electro-mechanical systems (MEMS) devices has proven to be costly and complex, and it has been a significant barrier to the commercialization of MEMS. We present a packaging solution applicable to several common MEMS devices, such as inertial sensors and micromechanical resonators. It involves deposition of a 20 /spl mu/m layer of epi-polysilicon over unreleased devices to act as a sealing cap, release of the encapsulated parts via an HF vapor release process, and a final seal of the parts in 7 mbar (700 Pa) vacuum. Two types of accelerometers, piezoresistive and capacitive sensing, were fabricated. Piezoresistive accelerometers with a footprint smaller than 3 mm/sup 2/ had a resolution of 10 /spl mu/g//spl radic/Hz at 250 Hz. Capacitive accelerometers with a 1 mm/sup 2/ footprint had a resolution of 1 mg/spl radic/Hz over its 5 kHz bandwidth. Resonators with a quality factor as high as 14,000 and resonant frequency from 50 kHz to 10 MHz have also been built. More than 100 capacitive accelerometers and 100 resonators were tested, and greater than 90% of the resonators and accelerometers were functional.

Method for forming a thin film using an atomic layer deposition (ALD) process

Abstract: A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.

GaN nanotip pyramids formed by anisotropic etching

Abstract: We experimentally demonstrate the formation of GaN nanotip pyramids by selective and anisotropic etching of N-polar GaN in KOH solution. For samples grown with adjacent Ga- and N-polar regions on the same wafer, the KOH solution was found to selectively etch only the N-polar surface while leaving the Ga-polar surface intact. An aggregation of hexagonal pyramids with well defined {10 1 1} facets and very sharp tips with diameters less than ∼20 nm were formed. The density of the pyramids can be controlled by varying the KOH concentration, solution temperature or the etch duration. The GaN etching activation energy is estimated to be Ea≈0.587 eV. Dense GaN pyramids with sharp tips have applications in both electronic and photonic devices.

Growth of large periodic arrays of carbon nanotubes

Abstract: Large periodic arrays of carbon nanotubes have been grown by plasma-enhanced hot filament chemical vapor deposition on periodic arrays of nickel dots that were prepared by polystyrene nanosphere lithography. A single layer of self-assembled polystyrene spheres was first uniformly deposited on a silicon wafer as a mask, and then electron beam vaporization was used to deposit a nickel layer through the mask. The size of and spacing between the nickel dots are tunable by varying the diameter of the polystyrene spheres, which consequently determines the diameter and site density of carbon nanotubes. The technique can be scaled up at much lower cost than electron beam lithography.

Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography

Abstract: A photolithography-based method capable of size reduction to produce sub-10-nm Si nanowire arrays on a wafer scale is described. By conformally depositing a material (silicon oxide or silicon) that...

Low‐Temperature Wafer‐Scale Production of ZnO Nanowire Arrays.

Abstract: Since the first report of ultraviolet lasing from ZnO nanowires, substantial effort has been devoted to the development of synthetic methodologies for one-dimensional ZnO nanostructures. Among the various techniques described in the literature, evaporation and condensation processes are favored for their simplicity and high-quality products, but these gas-phase approaches generally require economically prohibitive temperatures of 800–900 8C. Despite recent MOCVD schemes that reduced the deposition temperature to 450 8C by using organometallic zinc precursors, the commercial potential of gas-phase-grown ZnO nanowires remains constrained by the expensive and/or insulating (for example, Al2O3) substrates required for oriented growth, as well as the size and cost of the vapor deposition systems. A low-temperature, large-scale, and versatile synthetic process is needed before ZnO nanowire arrays find realistic applications in solar energy conversion, light emission, and other promising areas. Solution approaches to ZnO nanowires are appealing because of their low growth temperatures and good potential for scale-up. In this regard, Vayssieres et al. developed a hydrothermal process for producing arrays of ZnO microrods and nanorods on conducting glass substrates at 95 8C. Recently, a seeded growth process was used to make helical ZnO rods and columns at a similar temperature. Here we expand on these synthetic methods to produce homogeneous and dense arrays of ZnO nanowires that can be grown on arbitrary substrates under mild aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two-inch plastic substrates, which demonstrate the ease of commercial scale-up. The simple two-step procedure yields oriented nanowire films with the largest surface area yet reported for nanowire arrays. The growth process ensures that a majority of the nanowires in the array are in direct contact with the substrate and provide a continuous pathway for carrier transport, an important feature for future electronic devices based on these materials. Well-aligned ZnO nanowire arrays were grown using a simple two-step process. In the first step, ZnO nanocrystals (5–10 nm in diameter) were spin-cast several times onto a four-inch Si(100) wafer to form a 50–200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 150 8C to ensure particle adhesion to the wafer surface. The ZnO nanocrystals were prepared according to the method of Pacholski. A NaOH solution in methanol (0.03m) was added slowly to a solution of zinc acetate dihydrate (0.01m) in methanol at 60 8C and stirred for two hours. The resulting nanoparticles are spherical and stable for at least two weeks in solution. After uniformly coating the silicon wafer with ZnO nanocrystals, hydrothermal ZnO growth was carried out by suspending the wafer upside-down in an open crystallizing dish filled with an aqueous solution of zinc nitrate hydrate (0.025m) and methenamine or diethylenetriamine (0.025m) at 90 8C. Reaction times spanned from 0.5 to 6 h. The wafer was then removed from solution, rinsed with deionized water, and dried. A field-emission scanning electron microscope (FESEM) was used to examine the morphology of the nanowire array across the entire wafer, while single nanowires were characterized by transmission electron microscopy (TEM). Nanowire crystallinity and growth direction were analyzed by X-ray diffraction and electron diffraction techniques. SEM images taken of several four-inch samples showed that the entire wafer was coated with a highly uniform and densely packed array of ZnO nanowires (Figure 1). X-ray diffraction (not shown) gave a wurtzite ZnO pattern with an enhanced (002) peak resulting from the vertical orientation of the nanowires. A typical synthesis (1.5 h) yielded wires with diameters ranging between 40–80 nm and lengths of 1.5–2 mm.

Method and apparatus for supporting a semiconductor wafer during processing

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.