There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Advancing perovskite solar cell technologies toward their theoretical power conversion efficiency (PCE) requires delicate control over the carrier dynamics throughout the entire device. By controlling the formation of the perovskite layer and careful choices of other materials, we suppressed carrier recombination in the absorber, facilitated carrier injection into the carrier transport layers, and maintained good carrier extraction at the electrodes. When measured via reverse bias scan, cell PCE is typically boosted to 16.6% on average, with the highest efficiency of ~19.3% in a planar geometry without antireflective coating. The fabrication of our perovskite solar cells was conducted in air and from solution at low temperatures, which should simplify manufacturing of large-area perovskite devices that are inexpensive and perform at high levels.

http://science.sciencemag.org/content/sci/345/6196/542.full.pdf

Interface engineering of highly efficient perovskite solar cells

A novel non-fullerene electron acceptor (ITIC) that overcomes some of the shortcomings of fullerene acceptors, for example, weak absorption in the visible spectral region and limited energy-level variability, is designed and synthesized. Fullerene-free polymer solar cells (PSCs) based on the ITIC acceptor are demonstrated to exhibit power conversion effi ciencies of up to 6.8%, a record for fullerene-free PSCs.

An electron acceptor challenging fullerenes for efficient polymer solar cells.

In this work, we utilize electron-phonon Monte Carlo simulations of AlGaN/GaN HEMTs to determine the energy loss rate of electrons in the channel of the transistor as a function of bias conditions. Intense energy transfer from electrons to phonons is observed near the gate edge on the drain side of such devices where the peak electric field exists. This intense energy exchange results in nanometer sized hotspots in the vicinity of the gate edge. In order to account for effects of ballistic phonon transport on temperature near the hotspots, a non-gray Discrete Ordinates Method (DOM) is used as a numerical solver for the phonon Boltzmann Transport Equation (BTE). The non-gray model accounts for dispersion effects of GaN by splitting the dispersion curve of GaN into a finite number of frequency bands. The phonons in each frequency band are assumed to have the same properties with the other phonons in the same band and the relaxation times between these bands are calculated. The results show how energy is redistributed among the available phonon bands and demonstrates which modes are most effective at transporting the thermal energy. Finally, the hotspot temperature predictions obtained by the model are compared to temperatures obtained by gray and continuum modeling approaches to show the discrepancies between different techniques.Copyright © 2012 by ASME

Modeling the Hotspot Temperature in AlGaN/GaN High Electron Mobility Transistors Using a Non-Gray Phonon BTE Solver

Phonon Mean Free Path and Thermal Conductivity Relation for Gallium Nitride

Power electronics devices can be limited in operation, and lifetime by the ability to remove heat and maintain low junction temperatures. A common architecture for power electronics devices is a circuit soldered onto a direct-bonded-copper (DBC) substrate, which is attached to a heat spreader or and heat sink. The removal of some of these interfaces and materials, however, can reduce the overall thermal resistance and allow for the devices to operate at much higher power levels. One approach to do this is to directly cool the backside of the DBC power substrate. By sintering copper particles to the DBC, evaporative cooling can be integrated into the architecture without the need for another bond. In this study heat fluxes up to 75 W/cm2 were applied through a test chip attached to a 15 mm × 17 mm DBC substrate with varying thicknesses of sintered copper particles on the backside. The copper porous layer was partially submerged into deionized (DI) water in order to allow for capillary wicking and evaporative cooling from the backside. Heat was dissipated through the thermal test chip, while the junction temperature was measured. The surface temperature of the porous copper layer was measured with a FLIR thermal camera. From this set-up the evaporative heat transfer coefficient (HTC) was computed and the thermal resistance calculated. The thermal resistance was found to be in good agreement with numerical models. Overall, the thermal resistance was reduced by about half when compared to the conventional packaging design.

Cooling of power electronics by integrating sintered Cu particle wick onto a direct-bond copper substrate

Successful commercialization of flexible organic electronic devices is largely dependent on proper encapsulation that protects them from permeation of oxygen and water vapor. At present, low permeation encapsulation materials generally consist of multilayer films of organic/inorganic materials which can be deposited by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and vapor phase deposition. For this study, we report the effective water vapor transmission rates (WVTR) for multilayer thin films consisting of low temperature PECVD deposited SiNx and SiOx combined with a parylene organic layer. The effective WVTR was measured as a function of the number of bilayer pairs using Ca corrosion tests. The effective WVTR at 20 °C and 50% relative humidity [RH] for three bilayer pairs of SiOx/parylene ranged between 4.4–8.0 × 10−4 g/m2 /day while SiNx/parylene had a transmission rate 1.3×10−4 g/m2 /day. In general, additional layers were found to decrease the permeation rates to as low as 3.9×10−5 g/m2 /day, while the SiNx/parylene coatings performed the best overall.© 2007 ASME

Fabrication and Characterization of SiOx/Parylene and SiNx/Parylene Thin Film Encapsulation Layers

Provided are an evaporating device including porous media and a method of manufacturing the evaporating device. The evaporating device includes a porous media and is configured to evaporate a working fluid, wherein the porous media is formed by sintering sinter particles and includes many pores, wherein a nanoparticle coating layer in which nanoparticles having a size of 10 nm to 30 nm are joined is formed on surfaces of the sinter particles. The method includes: sintering sinter particles to form porous media having many pores therein; and forming a nanoparticle coating layer on surfaces of the sinter particles forming the porous media by using nanoparticles having a size of 10 nm to 30 nm.

Samuel Graham

Papers

Modeling the Hotspot Temperature in AlGaN/GaN High Electron Mobility Transistors Using a Non-Gray Phonon BTE Solver

Phonon Mean Free Path and Thermal Conductivity Relation for Gallium Nitride

Cooling of power electronics by integrating sintered Cu particle wick onto a direct-bond copper substrate

Fabrication and Characterization of SiOx/Parylene and SiNx/Parylene Thin Film Encapsulation Layers

Evaporating device having porous media and method for manufacturing thereof