There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Advancing perovskite solar cell technologies toward their theoretical power conversion efficiency (PCE) requires delicate control over the carrier dynamics throughout the entire device. By controlling the formation of the perovskite layer and careful choices of other materials, we suppressed carrier recombination in the absorber, facilitated carrier injection into the carrier transport layers, and maintained good carrier extraction at the electrodes. When measured via reverse bias scan, cell PCE is typically boosted to 16.6% on average, with the highest efficiency of ~19.3% in a planar geometry without antireflective coating. The fabrication of our perovskite solar cells was conducted in air and from solution at low temperatures, which should simplify manufacturing of large-area perovskite devices that are inexpensive and perform at high levels.

http://science.sciencemag.org/content/sci/345/6196/542.full.pdf

Interface engineering of highly efficient perovskite solar cells

A novel non-fullerene electron acceptor (ITIC) that overcomes some of the shortcomings of fullerene acceptors, for example, weak absorption in the visible spectral region and limited energy-level variability, is designed and synthesized. Fullerene-free polymer solar cells (PSCs) based on the ITIC acceptor are demonstrated to exhibit power conversion effi ciencies of up to 6.8%, a record for fullerene-free PSCs.

An electron acceptor challenging fullerenes for efficient polymer solar cells.

The ability to fabricate AlGaN/GaN high electron mobility transistors (HEMTs) on Si substrates has enabled the production of low cost high power electronics. To further enhance the performance of GaN electronics for high power conversion, the ability to maintain high off-state breakdown voltages with large electron densities is necessary. The use of Si substrates, however, limits the device's capabilities due to its weak electrical field strength. This limitation has been identified as the main cause for breakdown in HEMTs when the high electric field reaches the silicon substrate underneath the region between the gate and drain. To overcome this obstacle, removal of the Si substrate between the gate and drain region has shown to increase the device's breakdown voltage up to 3000 V. While removing the Si substrate extends the capabilities of GaN HEMTs for high voltage applications, the effects of the Si removal on the thermal performance during operation has not yet been investigated. Raman Thermometry, a well-developed technique, is used to compare the maximum temperature rise between a Local Substrate Removed (LSR) device and a non-LSR device. The application of nanoparticles (TiO2 and ZnO) for measuring surface temperatures via Raman spectroscopy is also investigated and applied to determine a more accurate temperature of the gate junction temperature. The LSR device was found to have a much higher thermal resistance than its non-LSR device counterpart limiting the maximum power dissipation the LSR device can achieve before severe degradation. Volumetric averaged residual stress mapping was also measured via Raman Spectroscopy and suggests the removal of the Si relaxes the stress in the GaN buffer layer and AlGaN barrier which can be exploited in designs to improve reliability. Methods to improve the thermal reliability of LSR devices are key to implementing such devices as future power switches.

The thermal effects of substrate removal on GaN HEMTs using Raman Thermometry

Particle rotations during plastic deformation of 5086 aluminum alloy

This paper explores high-speed image capture as a viable approach for non-invasive thermal analysis. The ability to monitor thermal transients and obtain accurate spatial information for miniature devices is important for many lighting applications. In this study, high power optoelectronic devices are stressed, and the impact of self-heating effects is examined. Results demonstrate that these effects lead to degraded device performance, reduced efficiency, and power loss.

High-speed thermal analysis of high power diode arrays

<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-phase gallium oxide (<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga2O3) is drawing significant attention in the power electronics field due to its remarkable critical electric field strength [greater than gallium nitride (GaN) and silicon carbide (SiC)] and the availability of high-quality melt-grown substrates providing the opportunity for low-cost manufacturing. However, because of the low thermal conductivity of <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga2O3, thermal management strategies at the device-level are required to achieve the targeted high-power capabilities. In this work, the effects of the anisotropic thermal conductivity of <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga2O3 and the geometrical design of the metal electrodes/interconnects on the device self-heating were investigated. For a power density (<inline-formula> <tex-math notation="LaTeX">${P}_{\text {dis}}$ </tex-math></inline-formula>) of 1 W/mm at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS}} =$ </tex-math></inline-formula> 4 V (i.e., a fully open channel condition), when the channel width is along a direction perpendicular to (<inline-formula> <tex-math notation="LaTeX">$\bar {{2}}{01}$ </tex-math></inline-formula>), the channel temperature decreases by 10% as compared to a case aligning the channel length along the direction close to [100]. Also, by decreasing the width of the interconnect between the drain electrode and the metal bond pad (serving as a heat pathway) from 100 to <inline-formula> <tex-math notation="LaTeX">$10~\mu \text{m}$ </tex-math></inline-formula> (90% reduction), the channel temperature increased by ~8% for <inline-formula> <tex-math notation="LaTeX">${P}_{\text {dis}} =$ </tex-math></inline-formula> 1 W/mm. Last, for devices with identical heat generation profiles, increasing the distance between the gate and drain contact from 1 to 10 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, results in a 35% increase in the channel temperature rise. This work highlights the importance of thermally aware device layout design for lateral <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga2O3 transistors, in terms of maximizing both the electrical and thermal performance.

Thermally-Aware Layout Design of β-Ga₂O₃ Lateral MOSFETs

Transient thermoreflectance imaging (TTI) is a thermometry technique employed to map the surface temperature distribution of GaN HEMTs. The accuracy of the technique is dependent on applying the correct thermoreflectance coefficient to the region of interest on the device surface. TTI has shown high accuracy when measuring the temperature rise of metals such as Schottky contacts but the technique has never been verified when applied to semiconductors. Using UV LED excitation sources, TTI of the GaN channel in GaN/Si HEMTs is presented and verified for the first time via the comparison of the gate metal temperature. A pixel by pixel calibration method is implemented to improve the spatial accuracy and account for any variability in the thermoreflectance coefficient across the device. The improvements of TTI discussed in this study make the technique an accurate and effective method to measure the temperature distribution of both the gate metal and GaN.

Samuel Graham

Papers

The thermal effects of substrate removal on GaN HEMTs using Raman Thermometry

Particle rotations during plastic deformation of 5086 aluminum alloy

High-speed thermal analysis of high power diode arrays

Thermally-Aware Layout Design of β-Ga₂O₃ Lateral MOSFETs

Improving the Transient Thermal Characterization of GaN HEMTs