Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Method and system for improvement of dose correction for particle beam writers

Abstract: A method and system for dose correction of a particle beam writer is disclosed. The method and system includes reading a file of writing objects that includes dose intensity, calculating a rate of dose intensity change between adjacent writing objects, selecting a writing object that may need accuracy improvement of dose correction based on the rate of dose intensity change, and improving accuracy of the dose correction of the writing object that is selected and its adjacent objects.

Optimal 2-D cell layout with integrated transistor folding

Abstract: Folding, a key requirement in high performance cell layout, implies breaking a large transistor into smaller, equal sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique, FCLIP, that integrates folding into the generation of optimal layouts of CMOS cells in the two dimensional (2D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors, We then extend FCLIP to accommodate-and-stack clustering, a requirement in most practical designs due to its benefits to circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP based approach in easily accommodating additional design constraints.

Method and system for lithography simulation and measurement of critical dimensions with improved CD marker generation and placement

Abstract: A method and system for lithography simulation and measurement of critical dimensions with improved CD marker generation and placement is disclosed. The method and system specify a position for measuring a difference between a lithography image and a target pattern, generate one or more CD marker candidates, and select at least one CD marker from the one or more CD marker candidates.

Fast pattern matching

Abstract: Disclosed are methods, systems, and articles of manufacture for using pattern matching with an integrated circuit layout including recognizing shapes within the IC layout, identifying features for the shapes, and extracting situations for the respective features. The method may further include simulating the situations to determine a set of situations for modification based on an OPC requirement, modifying the set of situations to improve satisfaction of the OPC requirement, and reintegrating the modified set of situations into the IC layout. The method may also include simulating a subset of the extracted situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. The method may also include removing overlap from a window based on the situations extracted for the window, calculating a density for each of the situations, and calculating a density for the window based on the density.

System and method for performing design verification

Abstract: A design verification system for developing electronic systems and methods for manufacturing and using same. The design verification system comprises a plurality of system elements, including at least one physical (or hardware) element and/or at least one virtual (or software) element, which are coupled, and configured to communicate, via a general communication system. Since the system elements may be provided on dissimilar development platforms, each system element is coupled with the communication system via a co-verification interface, which is provided as a layered protocol stack to assure portability and flexibility. Through use of the co-verification interface, the design verification system can be configured to support a wide variety of mixed physical/virtual systems.