Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Automatic placement of decoupling capacitors

Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

Method for correcting position-dependent distortions in patterning of integrated circuits

Abstract: A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.

Method and apparatus for performing an exponential path search

Abstract: Some embodiments of the invention provide a method of searching for a path. The method identifies a set of source and target elements. It then performs a path search that iteratively identifying path expansions in order to identify a set of associated path expansions that connect the source and target elements. The method costs at least one expansion based on an exponential equation that has an exponent that includes a cost associated with the expansion.

Method for analyzing path delays in an IC clock tree

Abstract: A macro-cell is incorporated into an integrated circuit (IC) design to describe a fixed arrangement of cells to be included in the IC. The IC includes a clock tree for delivering a clock signal from its root to all clocked devices (sinks) within the IC external to the macro-cell, and to a root of a clock tree subtree included within the macro-cell for delivering the clock signal from its root to sinks residing within the macro-cell. A model of the subtree depicts the maximum and minimum delays of the clock signal's rising and falling edges between the subtree root and the sinks within the macro-cell as functions of the clock signal's rising and falling edge transition times as they arrives at the subtree root and also as functions of the relative amount of delay the rising and falling edges experience as they pass from the clock tree root to the subtree root. A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signal's rising and falling edges as they pass from the clock tree root to any sink of the IC.

Energy and peak-current per-cycle estimation at RTL

Abstract: We present novel macromodeling techniques for estimating the energy dissipated and peak-current drawn in a logic circuit for every input vector pair (we call this the energy-per-cycle and peak-current-per-cycle, respectively). The macromodels are based on classifying the input vector pairs on the basis of their Hamming distances and using a different equation-based macromodel for every Hamming distance. The variables of our macromodel are the zero-delay transition counts at three logic levels inside the circuit. We present an automatic characterization process by which such macromodels can be constructed. The energy-per-cycle macromodel provides a transient energy waveform, and can also be used to estimate the moving average energy over any time window, whereas peak-current-per-cycle macromodel provides peak-current which can be used for studying IR drop problems. Some key features of this technique are: 1) the models are compact (linear in the number of inputs); 2) they can be used for any input sequence; and 3) the characterization is automatic and requires no user intervention. These approaches have been implemented and models have been built and tested for many circuits. The average errors observed in estimating the energy-per-cycle and peak-current-per-cycle are under 20%. The energy-per-cycle model can also be used to measure the long-term average power, with an observed error of under 10% on average.