Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

ePlace-3D: Electrostatics based Placement for 3D-ICs

Abstract: We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) 3D numerical solution with improved spectral formulation (3) 3D nonlinear pre-conditioner for convergence acceleration (4) interleaved 2D-3D placement for efficiency enhancement. Our placer outperforms the leading work mPL6-3D and NTUplace3-3D with 6.44% and 37.15% shorter wirelength, 9.11% and 10.27% fewer 3D vertical interconnects (VI) on average of IBM-PLACE circuits. Validation on the large-scale modern mixed-size (MMS) 3D circuits shows high performance and scalability.

Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20

Abstract: In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows The approach does not require restrictions on the design of the chip This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout It will demonstrate examples of over-constrained layouts and how these configurations are mitigated It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown Lithography results are shown with effective k1<02 for logic and flash memory patterns

A unified framework for simultaneous layout decomposition and mask optimization

Abstract: In advanced technology nodes, layout decomposition and mask optimization are two key stages in integrated circuit design. Due to the inconsistency of the objectives of these two stages, the performance of conventional layout and mask optimization may be suboptimal. To tackle this problem, in this paper we propose a unified framework, which seamlessly integrates layout decomposition and mask optimization. We propose a gradient based approach to solve the unified mathematical formulation, as well as a set of discrete optimization techniques to avoid being stuck in local optimum. The conventional optimization process can be accelerated as some inferior decompositions can be smartly pruned in early stages. The experimental results show that the proposed unified framework can achieve more than 17 x speed-up compared with the conventional two-stage flow, meanwhile it can reduce EPE violations by 18%, and thus maintain better design quality.