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Institution

Cadence Design Systems

CompanySan Jose, California, United States
About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.


Papers
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Patent
27 Jun 2012
TL;DR: In this paper, the authors describe an approach for allowing electronic design, verification and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing.
Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

33 citations

Patent
17 Jul 1998
TL;DR: In this paper, a method and system for combinational verification tightly integrates multiple verification methods, such as SAT-based analysis, random simulation, and SATbased analysis on two combinational netlists.
Abstract: A method and system for combinational verification tightly integrates multiple verification methods. The present invention performs random simulation on the inputs of two combinational netlists. The nets within the netlists are described as BDDs and divided into classes of cutpoint candidates based upon the signatures produced by the random simulation. Cutpoint candidates within each class are resolved to determine whether the candidates are equivalent. If the nets are likely to be equivalent, BDD composition is performed on the nets. Otherwise, SAT-based analysis is performed on the nets. If either method fails to resolve the cutpoints within an allocated amount of time or resources, then the other method is invoked and information learned by the first method is passed to the second method to assist in the resolution. This process repeats until the cutpoint candidates are resolved. If the cutpoint resolution produces a true negative, then the candidate classes are refined by performing directed simulation on the inputs of the netlists using the witness to the true negative generated by the cutpoint resolution. This directed simulation produces new candidate classes that are resolved as described above. If, after the cutpoint classes are refined, the outputs are in a different class, then the netlists are unequal. If a false negative is found after the cutpoints are resolved, a new cutpoint is created. If the outputs are in the current class, then the two netlists are equal. Otherwise, the cutpoints are further resolved as described above.

33 citations

Journal ArticleDOI
TL;DR: This data indicates a relationship between the antiseptic agent used for skin preparation at time of CIED procedure and risk for infection and that this relationship should be investigated further.
Abstract: Background: Cardiac implantable electronic device (CIED) infection is a major complication that is associated with increased morbidity and mortality. Recent data suggested a relationship between the antiseptic agent used for skin preparation at time of CIED procedure and risk for infection. Methods: On April 30, 2011, we changed the antiseptic agent used for skin preparation at our tertiary care facility from chlorhexidine-alcohol to povidone-iodine for all CIED procedures. We retrospectively reviewed records of all patients who underwent CIED procedure 1 year before and after the change. CIED infection was defined as pocket or endovascular systemic infection that required removal within 1 year of the index procedure. We examined if the change affected the risk of CIED infection. Results: A total of 2,792 patients underwent 2,840 CIED procedures; 1,748 (61.5%) had implantable cardioverter defibrillator procedures and 1,092 (38.4%) had permanent pacemaker procedures. Chlorhexidine-alcohol agent was used in 1,450 (51.1%) procedures, and povidone-iodine agent was used in 1,390 (48.9%). After 1 year of follow-up, 31 patients (1.09%) developed CIED infection that required system removal. The 1-year infection rate was 1.1% among both antiseptic agent groups and there were no significant differences in the infection presentations among both groups (P = 0.950). Multivariate Cox proportional hazards regression model showed that risk factors for infection within 1 year included age, diabetes, and African American race. Conclusion: In one large cohort of patients undergoing CIED procedures, the antiseptic agent used for skin preparation (chlorhexidine-alcohol vs povidone-iodine) was not associated with increased risk of developing CIED infection. (PACE 2014; 00:1‐7) Cardiac implantable electronic device, pacemaker, defibrillator, infection, complication, outcome

33 citations

Journal ArticleDOI
05 Feb 1998
TL;DR: In this paper, the design and implementation of an 8-order bandpass delta-sigma modulator is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations.
Abstract: This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-/spl mu/m BiCMOS process and occupies an active area of 1.7 mm/sup 2/. Operating from /spl plusmn/2.5-V supplies, the fabricated prototype exhibits stable behaviour and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order single-bit bandpass delta-sigma modulation.

33 citations

Proceedings ArticleDOI
24 Jan 2006
TL;DR: How OA improves interoperability among applications in an EDA flow is described and how OA benefits developers of both EDA tools and flows is detailed.
Abstract: The OpenAccess database provides a comprehensive open standard data model and robust implementation for IC design flows. This paper describes how it improves interoperability among applications in an EDA flow. It details how OA benefits developers of both EDA tools and flows. Finally, it outlines how OA is being used in the industry, at semiconductor design companies, EDA tool vendors, and universities.

33 citations


Authors

Showing all 3142 results

NameH-indexPapersCitations
Alberto Sangiovanni-Vincentelli9993445201
Derong Liu7760819399
Andrew B. Kahng7661824097
Jason Cong7659424773
Kenneth L. McMillan6015020835
Edoardo Charbon6052612293
Richard B. Fair5920514653
John P. Hayes5830211206
Sachin S. Sapatnekar5642412543
Wayne G. Paprosky5619610571
Robert G. Meyer4911613011
Scott M. Sporer491508085
Charles J. Alpert492248287
Joao Marques-Silva482899374
Paulo Flores483217617
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
2021103
2020185
2019212
2018103
201788