Institution
Cadence Design Systems
Company•San Jose, California, United States•
About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.
Topics: Circuit design, Routing (electronic design automation), Integrated circuit, Integrated circuit design, Physical design
Papers published on a yearly basis
Papers
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18 Jan 2001TL;DR: In this paper, the system and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed, and one preferred method of designing an integrated circuit includes several steps.
Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.
40 citations
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TL;DR: In this article, an application of the methodology and of the various software tools embedded in the POLIS co-design system is presented in the realm of automotive electronics: a shock absorber controller, whose specification comes from an actual product.
Abstract: We present an application of the methodology and of the various software tools embedded in the POLIS co-design system. The application is in the realm of automotive electronics: a shock absorber controller, whose specification comes from an actual product. All aspects of the design process are closely examined, including high level language specification and automatic hardware and software synthesis. We analyze different software implementation styles, compare the results, and outline the future developments of our work.
40 citations
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22 Jun 2009TL;DR: In this paper, the authors present methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits and provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams.
Abstract: Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.
40 citations
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06 Apr 2003TL;DR: This work proposes DME/BST based algorithms for clock tree routing to improve skew tolerance to process variations and demonstrates great improvement on process variation tolerance through the algorithms.
Abstract: Fast progress on VLSI technology makes clock skew more susceptible to process variations. We propose DME/BST based algorithms for clock tree routing to improve skew tolerance to process variations. The worst case skew due to process variations is estimated and employed to guide the decision making during the routing. Our method can be applied to general non-zero skew requirements. Minimizing total wirelength is considered as a secondary objective at the same time. Experimental results on benchmark circuits demonstrate great improvement on process variation tolerance through our algorithms.
40 citations
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29 Nov 2010TL;DR: In this paper, the authors provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints by extending a region from the error marked region to extract a pattern for decomposition analysis.
Abstract: Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analysis. Some embodiments compare the extracted pattern to known patterns stored in a library, which also stores at least one previously computed decomposition solution for each known pattern. For an extracted pattern existing within the library, some embodiments retrieve the previously computed decomposition solution from the library. For an extracted pattern that does not exist within the library, some embodiments use one or more simulations to determine a decomposition solution for the extracted pattern. The resulting decomposition solution replaces the extracted pattern within the design layout producing a variant of the original layout that contains the decomposed solution for the pattern.
40 citations
Authors
Showing all 3142 results
Name | H-index | Papers | Citations |
---|---|---|---|
Alberto Sangiovanni-Vincentelli | 99 | 934 | 45201 |
Derong Liu | 77 | 608 | 19399 |
Andrew B. Kahng | 76 | 618 | 24097 |
Jason Cong | 76 | 594 | 24773 |
Kenneth L. McMillan | 60 | 150 | 20835 |
Edoardo Charbon | 60 | 526 | 12293 |
Richard B. Fair | 59 | 205 | 14653 |
John P. Hayes | 58 | 302 | 11206 |
Sachin S. Sapatnekar | 56 | 424 | 12543 |
Wayne G. Paprosky | 56 | 196 | 10571 |
Robert G. Meyer | 49 | 116 | 13011 |
Scott M. Sporer | 49 | 150 | 8085 |
Charles J. Alpert | 49 | 224 | 8287 |
Joao Marques-Silva | 48 | 289 | 9374 |
Paulo Flores | 48 | 321 | 7617 |