Institution
Cadence Design Systems
Company•San Jose, California, United States•
About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.
Topics: Circuit design, Routing (electronic design automation), Integrated circuit, Integrated circuit design, Physical design
Papers published on a yearly basis
Papers
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20 Jul 2001TL;DR: In this paper, the authors propose a wireless bridge extension that allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to another without losing its back end connection.
Abstract: A Wireless bridge conjoins two previously incompatible technologies within a single device to leverage the strengths of each. The Wireless bridge marries the Personal Area Network (PAN) technology of Bluetooth as described in Bluetooth Specification Version 1.0B with the Wireless Local Area Network (WLAN) technology described in the IEEE802.11a specification to provide a wireless system level solution for peripheral devices to provide Internet service interactions. The invention brings together in a single working device implementations of these technologies so they do not interfere or disrupt the operation of each other and instead provide a seamless transition of a Bluetooth connection to Wireless Local Area Network/Internet connection. From the Wireless Local Area Network perspective the inventive wireless bridge extension allows a Bluetooth-enabled device to roam from one Wireless Access Point (bridge) to the next without losing its back end connection. The invention takes into account the minimum separation and shielding required of these potentially conflicting technologies to inter-operate.
273 citations
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07 Apr 2003TL;DR: In this paper, a method of automatic abstraction is presented that uses proofs of unsatisfiability derived from SAT-based bounded model checking as a guide to choosing an abstraction for unbounded model checking.
Abstract: A method of automatic abstraction is presented that uses proofs of unsatisfiability derived from SAT-based bounded model checking as a guide to choosing an abstraction for unbounded model checking. Unlike earlier methods, this approach is not based on analysis of abstract counterexamples. The performance of this approach on benchmarks derived from microprocessor verification indicates that SAT solvers are quite effective in eliminating logic that is not relevant to a given property. Moreover, benchmark results suggest that when bounded model checking successfully terminates, and the problem is unsatisfiable, the number of state variables in the proof of unsatisfiability tends to be small. In almost all cases tested, when bounded model checking succeeded, unbounded model checking of the resulting abstraction also succeeded.
261 citations
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14 Jul 2003TL;DR: In this article, a method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit's design data to inspect a mask, based on which a mask can be inspected.
Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
258 citations
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TL;DR: How emerging FPGA technology's unique combination of size and power efficiency plus field programmability offers a transition of FPCAs from ASIC prototyping to embedded products is described.
Abstract: As new radio standards are deployed without substantially supplanting existing ones, the need for multimode multiband handsets and infrastructure increases. This article describes how emerging FPGA technology's unique combination of size and power efficiency plus field programmability offers a transition of FPCAs from ASIC prototyping to embedded products. Software-defined receiver examples suggest an enlarged role for FPGAs in pragmatic paths toward the productization of software radio technology.
256 citations
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TL;DR: This paper shows how to construct TBR-like methods that generate guaranteed passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.
Abstract: The major concerns in state-of-the-art model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms, such as PRIMA, generate guaranteed-passive models for systems with special internal structure, using numerically stable and efficient Krylov-subspace iterations. Truncated balanced realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper, we show how to construct TBR-like methods that generate guaranteed passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.
254 citations
Authors
Showing all 3142 results
Name | H-index | Papers | Citations |
---|---|---|---|
Alberto Sangiovanni-Vincentelli | 99 | 934 | 45201 |
Derong Liu | 77 | 608 | 19399 |
Andrew B. Kahng | 76 | 618 | 24097 |
Jason Cong | 76 | 594 | 24773 |
Kenneth L. McMillan | 60 | 150 | 20835 |
Edoardo Charbon | 60 | 526 | 12293 |
Richard B. Fair | 59 | 205 | 14653 |
John P. Hayes | 58 | 302 | 11206 |
Sachin S. Sapatnekar | 56 | 424 | 12543 |
Wayne G. Paprosky | 56 | 196 | 10571 |
Robert G. Meyer | 49 | 116 | 13011 |
Scott M. Sporer | 49 | 150 | 8085 |
Charles J. Alpert | 49 | 224 | 8287 |
Joao Marques-Silva | 48 | 289 | 9374 |
Paulo Flores | 48 | 321 | 7617 |