Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Method and apparatus for power consumption optimization for integrated circuits

Abstract: Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

Hotspot detection and design recommendation using silicon calibrated CMP model

Abstract: Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

Translating Software Designs for Model Checking

Abstract: This paper presents a systematic consideration of the major issues involved in translation of executable design level software specification languages to directly model-checkable formal languages. These issues are considered under the framework of integrated model/property translation and include: (1) translator architecture; (2) semantics translation from a software language to a formal language; (3) property specification and translation; (4) transformations for state space reduction; (5) translator validation and evolution. Solutions to these issues are defined, described, and illustrated in the context of translating xUML, an executable design level software specification language, to S/R, the input formal language of the COSPAN model checker.

Method and system for clock tree synthesis of an integrated circuit

Abstract: Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-based clock tree estimation, wherein each block is subdivided into one or more grids. The aspects further include merging of the estimated block-level clock tree structures with the top-level clock tree synthesis.

Cone slack allocator for computing time budgets

Abstract: Timing slack is allocated to edges of a timing graph by a converging loop that calls a Domain Restricted Timing Cone (DRTC) iterator. The DRTC iterator invokes a kernel program for each DRTC and computes time budgets for each edge. The time budgets are kept within established constraints of the corresponding DRTC. A timing verifier computes an amount of slack for each edge based on the time budget. An edge or arc of the timing graph is made permanent when the slack is less than a predetermined epsilon. The kernel program is based on any of a fast estimate, consideration of all time to end point (tte) and weight to endpoint (wte) pairs within the graph, and/or a set of tte wte pairs (or an envelope) that represent segments of a lowest slack to weight ratio.