Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations

Abstract: The continuous technology scaling brings about high-dimensional performance variations that cannot be easily captured by the traditional response surface modeling. In this paper we propose a new statistical regression (STAR) technique that applies a novel strategy to address this high dimensionality issue. Unlike most traditional response surface modeling techniques that solve model coefficients from over-determined linear equations, STAR determines all unknown coefficients by moment matching. As such, a large number of (e.g., 103~105) model coefficients can be extracted from a small number of (e.g., 102~103) sampling points without over-fitting. In addition, a novel recursive estimator is proposed to accurately and efficiently predict the moment values. The proposed recursive estimator is facilitated by exploiting the interaction between different moment estimators and formulating the moment estimation problem into a special form that can be iteratively solved. Several circuit examples designed in commercial CMOS processes demonstrate that STAR achieves more than 20times runtime speedup compared with the traditional response surface modeling.

Timing model extraction of hierarchical blocks by graph reduction

Abstract: A timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from a gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and the capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.

AES crypto chip utilizing high-speed parallel pipelined architecture

Abstract: In November 2001, the National Institute of Standards and Technology (NIST) of the USA chose the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm Since then, many hardware implementations have been proposed in literature We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture By using an efficient inter-round and intra-round pipeline design, our implementation achieves a high throughput of 2977 Gbit/s in encryption whereas the highest throughput reported in the literature is 2154 Gbit/s

Implicit enumeration of strongly connected components and an application to formal verification

Abstract: This paper first presents a binary decision diagram-based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experimental results suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency-matrix of the graphs. This paper then applies this SCC algorithm to solve the bad cycle detection problem encountered in formal verification. Experimental results show that our new bad cycle detection algorithm is typically significantly faster than the state-of-the-art, sometimes by more than a factor of ten.

Partitioning placement method and apparatus

Abstract: Some embodiments of the invention are placers that use lines that are not orthogonal with each other to calculate the costs of potential placement configurations. Some of these embodiments use non-orthogonal lines to measure congestion costs of potential placement configurations. For instance, some embodiments use non-orthogonal lines as cut lines that divide the IC layout into regions. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut lines.