Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Abstract: We propose an electrostatics-based placement algorithm for large-scale mixed-size circuits (ePlace-MS). ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixed-size placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of dc removal and the advantages over prior density functions. Nesterov’s method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength is set as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3, ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the 16 modern mixed-size benchmark circuits with the same runtime.

Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures

Abstract: A methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(NlogN) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for the nonlinear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.

Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology

Abstract: The effects of substrate resistances on the performance of 5.8-GHz low-noise amplifiers (LNAs) have been evaluated through a combination of experimental and simulation studies. The substrate resistive network for the LNA has been constructed by fabricating and measuring a test structure. The substrate resistances can be significantly affected by the die area and thickness, which raises a serious concern for on-wafer testing and optimization of circuits using the test results. The substrate resistances reduce the simulated gain by more than 10 dB and increase the noise figure by 2.7 dB. The simulation study has shown that the dominant substrate resistances are those associated with the bondpads. To reduce the effects of the substrate resistances, a ground-shielded bondpad structure, which consists of a Metal 2 pad and an n/sup +/ plug grounded shield separated by a composite oxide layer, has been developed. It reduces the resistance to ground to almost zero by conducting the signal away from the substrate to ground through the low-resistivity n/sup +/ plug layer. The pad structure in addition improves the interpad isolation by as much as 35 dB. However, to harness this isolation improvement, the inductance between the IC and PC board ground should be made small by using a low ground inductance package. Using this ground-shielded bondpad, the measured gain and noise figure of a 4.5-GHz tuned amplifier were improved by 10 and 2 dB, respectively, over the same circuit implemented using the conventional bondpad.

Risk of Hippocampal Metastases in Small Cell Lung Cancer Patients at Presentation and After Cranial Irradiation: A Safety Profile Study for Hippocampal Sparing During Prophylactic or Therapeutic Cranial Irradiation

Abstract: Purpose Neurocognitive impairment (NI) in patients with small cell lung cancer (SCLC) after whole brain radiation treatment (WBRT) is a significant cause of morbidity. Hippocampal avoidance (HA) during WBRT may mitigate or prevent NI in such patients. However, this has not been tested in SCLC patients. The estimated risk of metastases in the HA region (HM) in patients with SCLC at diagnosis or after WBRT is unknown. Our study aimed to determine the risk of HM in patients with SCLC and to assess correlated clinical factors. Methods and Materials Patients with SCLC who experienced brain metastases (BM) at presentation (de novo) or after WBRT treated at the Saskatoon Cancer Centre between 2005 and 2012 were studied. Relevant neuroimaging was independently reviewed by a neuroradiologist. HM was defined as metastases within 5 mm of the hippocampus. Logistic regression analysis was performed to assess correlation between various clinical variables and HM. Results Seventy eligible patients were identified. Of 59 patients presenting with de novo BM, 3 patients (5%, 95% confidence interval [CI]: 0%-10.7%) had HM. Collectively there were 359 (range, 1-33) de novo BM with 3 (0.8%, 95% CI: 0%-1.7%) HM deposits. Twenty patients experienced progression of metastatic disease in the brain after WBRT. Of the 20 patients, only 1 patient (5%, 95% CI: 0%-14.5%) experienced HM. On logistic regression, no factors significantly correlated with HM. Conclusion The overall incidence of HM before or after WBRT in SCLC patients is low, providing preliminary support for the safety of HA during planned clinical trials of HA-WBRT for SCLC.