Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Delay-optimal clustering targeting low-power VLSI circuits

Abstract: This paper presents a delay-optimal clustering algorithm for minimizing the power dissipation in a very large scale integration (VLSI) circuit. Traditional approaches for delay-optimal clustering are based on Lawler's clustering algorithm which makes no attempt to explore alternative clustering solutions that have the same delay but lower power implementations. Our algorithm implicitly enumerates alternate clusterings and selects a clustering solution which has the same delay, but the lowest power dissipation. For tree circuits, the proposed algorithm produces delay- and power-optimal clustering, whereas for nontree circuits it produces delay-optimal clustering with significantly reduced power dissipation. The proposed mechanism can be used to generate power minimized clusters for various applications such as preprocessing designs for partitioning, clustering logic during synthesis, etc. The mechanism can also be deployed hierarchically to generate circuit partitioning solutions directly.

Test masks for lithographic and etch processes

Abstract: A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.

Lithographic simulations using graphical processing units

Abstract: Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.

Efficient on-chip delay estimation for leaky models of multiple-source nets

Abstract: An algorithm for efficiently computing an Elmore approximation in a leaky RC tree which may contain any number of uniformly distributed RC segments is presented. This algorithm works in the frequency domain, and it owes much of its efficiency to the fact that intermediate results leftover from computation of the driving-point admittance approximation are reused. The algorithm for computing an Elmore approximation starts at the output of the active source gate and proceeds downstream, in a finite sequence of steps, to the input of a specified load gate. >

Method and system for routing

Abstract: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers.