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Institution

Cadence Design Systems

CompanySan Jose, California, United States
About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.


Papers
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Proceedings ArticleDOI
07 Nov 2011
TL;DR: It is shown that TPL layout decomposition is a more difficult problem than that for DPL, and a novel vector programming formulation is proposed which can simultaneously minimize conflict and stitch numbers and solve it through effective semidefinite programming (SDP) approximation.
Abstract: As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programming formulation for TPL layout decomposition which can simultaneously minimize conflict and stitch numbers. Since ILP has very poor scalability, we propose three acceleration techniques without sacrificing solution quality: independent component computation, layout graph simplification, and bridge computation. For very dense layouts, even with these speedup techniques, ILP formulation may still be too slow. Therefore, we propose a novel vector programming formulation for TPL decomposition, and solve it through effective semidefinite programming (SDP) approximation. Experimental results show that the ILP with acceleration techniques can reduce 82% runtime compared to the baseline ILP. Using SDP based algorithm, the runtime can be further reduced by 42% with some tradeoff in the stitch number (reduced by 7%) and the conflict (9% more). However, for very dense layouts, SDP based algorithm can achieve 140× speed-up even compared with accelerated ILP.

219 citations

Proceedings ArticleDOI
10 Jun 2002
TL;DR: This paper shows how to construct TBR-like methods that guarantee passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.
Abstract: The major concerns in state-of-the-art model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms such as PRIMA generate guaranteed-passive models, for systems with special internal structure, using numerically stable and efficient Krylov-subspace iterations. Truncated balanced realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper we show how to construct TBR-like methods that guarantee passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.

211 citations

Journal ArticleDOI
TL;DR: This is the first study to compare plasma and cerebrospinal fluid (CSF) pharmacokinetics of intravenous (IV), oral (PO), or rectal (PR) formulations of acetaminophen.
Abstract: Background: This is the first study to compare plasma and cerebrospinal fluid (CSF) pharmacokinetics of intravenous (IV), oral (PO), or rectal (PR) formulations of acetaminophen. Methods: Healthy male subjects (N = 6) were randomized to receive a single dose of IV (OFIRMEV®; Cadence) 1,000 mg (15 minute infusion), PO (2 Tylenol® 500 mg caplets; McNeil Consumer Healthcare), or PR acetaminophen (2 Feverall® 650 mg suppositories; Actavis) with a 1-day washout period between doses. The 1,300 mg PR concentrations were standardized to 1,000 mg. Acetaminophen plasma and CSF levels were obtained at T0, 0.25, 0.5, 0.75, 1, 2, 3, 4, and 6 hours. Results: IV acetaminophen showed earlier and higher plasma and CSF levels compared with PO or PR administration. CSF bioavailability over 6 hours (AUC0–6) for IV, PO, and PR 1 g was 24.9, 14.2, and 10.3 μg·h/mL, respectively. No treatment-related adverse events were reported. One subject was replaced because of premature failure of his lumbar spinal catheter. The mean CSF level in the IV group was similar to plasma from 3 to 4 hours and higher from 4 hours on. Absorption phase, variability in plasma, and CSF were greater in PO and PR groups than variability with IV administration. Conclusions: These results demonstrate that earlier and greater CSF penetration occurs as a result of the earlier and higher plasma peak with IV administration compared with PO or PR.

209 citations

Patent
06 Jun 2002
TL;DR: In this article, a multi-faceted design platform (104) acts as a tool for front-end hardware IC designers who design complex core base System on Chip (SoC).
Abstract: A multi-faceted design platform (104) acts as a tool for front-end hardware IC designers who design complex core base System on Chip. The design platform (104) uses a network such as the Internet (230) to search and gain access to previously designed virtual core blocks. The design platform (104) provides a means to select (306) and transfer (308) all relevant information regarding the selected virtual core blocks and allows the designer to immediately incorporate the virtual core block into the new SoC design. The design platform (104) further generates the appropriate source code files (320) for immediate use with a plurality of known verification tools to verify both the integration and connectivity of the virtual core blocks as well as the basic functionalities of the SoC design.

205 citations

Proceedings ArticleDOI
13 Jan 1997
TL;DR: This paper presents a new exciting hybrid approach, called the modular approach, for the efficient analysis of both static and dynamic fault trees, which provides a combination of BDD solution for static fault trees and Markov chain solution for dynamic fault Trees coupled with the detection of independent subtrees.
Abstract: Three commonly used analytical techniques for reliability evaluation are fault trees, binary decision diagrams (BDD) and Markov chains. Each of these techniques have advantages and disadvantages and the choice depends on the system being modeled. Fault trees have been found to be the most popular choice in terms of building an analytical model of a system. It provides a compact representation of the system and is easily understood by humans. However, fault trees lack the modeling power and solution time increases exponentially with the size of the system being modeled. In this paper, we present a new exciting hybrid approach, called the modular approach, for the efficient analysis of both static and dynamic fault trees. It provides a combination of BDD solution for static fault trees and Markov chain solution for dynamic fault trees coupled with the detection of independent subtrees. The algorithms used for modularization, integrating the results obtained from the separate solution of the independent modules (subtrees) and incorporating coverage modeling are discussed in detail in this paper. The modular approach is applied to an example system to demonstrate the potential of this research.

205 citations


Authors

Showing all 3142 results

NameH-indexPapersCitations
Alberto Sangiovanni-Vincentelli9993445201
Derong Liu7760819399
Andrew B. Kahng7661824097
Jason Cong7659424773
Kenneth L. McMillan6015020835
Edoardo Charbon6052612293
Richard B. Fair5920514653
John P. Hayes5830211206
Sachin S. Sapatnekar5642412543
Wayne G. Paprosky5619610571
Robert G. Meyer4911613011
Scott M. Sporer491508085
Charles J. Alpert492248287
Joao Marques-Silva482899374
Paulo Flores483217617
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
2021103
2020185
2019212
2018103
201788