Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

Symbol timing recovery method for low resolution multiple amplitude signals

Abstract: Symbol timing is performed by providing a histogram of samples of a signal for a predetermined number of symbol times. An average, weighted average, or other method is applied to determine an average timing for a max eye opening for each symbol time. The average max eye opening timing is applied to an edge detection of a currently received signal to determine timing of a sample that is most likely to occur closest to the max eye opening for the current symbol. The invention may also be practiced based on a center timing of each symbol.

Towards Industrial Strength Business Performance Management

Abstract: Business performance management today does not possess a rigorous and grounded engineering methodology capable of delivering reliably measured values to backing up decision making. Much more it is the art of executive gurus who listen to their backbone experience and take their decisions using intuitive and heuristic approaches. This vagueness appears to be one of the main reasons for current dissatisfaction in industry. In this paper we express our vision of how a rigorous engineering methodology for business performance management in engineering design may look like. Our research work in PSI and PRODUKTIV+ projects strongly suggests that the underlying modeling framework has to be holonic. We consider that the solution has to: (i) be based on a sound Domain ontology of performance; (ii) use dynamic distributed planning technique and simulations to predict the performance of a design system; (iii) use the methodology which is sensitive to the specificities of a particular design system.

System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design

Abstract: A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

Practices in Mixed-Signal and RF IC Testing

Abstract: Mixed-signal (analog and digital) testing and RF testing pose major cost and quality challenges to the development of high-speed wired and wireless network and communication ICs. This article presents a brief overview of common industry practices for testing mixed-signal and RF ICs. We also present examples of DFT and BIST techniques for wired and wireless transceivers. Finally, we discuss the testing challenges of system-in-package (SiP) products and selected DFT approaches in use today.

Method and system for implementing abstract layout structures with parameterized cells

Abstract: An improved method and system are disclosed for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). One significant advantage is that abstracted versions of pcells can be generated from normal pcells and stored in a pcell cache, which avoids the need to abstract layout pcells on the fly.