Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

A memory-optimal buffering protocol for preservation of synchronous semantics under preemptive scheduling

Abstract: Recently, we have proposed a set of buffering schemes to preserve the semantics of a synchronous program when the latter is implemented as a set of multiple tasks running under preemptive scheduling. These schemes, however, are not optimal in terms of memory (buffer usage). In this paper we propose a new protocol which generalizes the previous schemes. The new protocol is not only semantics-preserving but also memory-optimal in two senses: first, in terms of the number of buffers required to preserve semantics in the worst case (i.e.,for the "worst" possible arrival/execution pattern of the tasks); second, in terms of the number of buffers required to preserve semantics for any arrival/execution pattern and at any time, assuming no knowledge of future arrivals.

The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme

Abstract: This paper reviews the most critical components of a ‘holistic’ DTCO flow for an advanced technology node and in doing so quantifies the differences between 7nm technology node definitions implemented with extreme ultraviolet and 193nm immersion lithography. The DTCO topics covered include: setting scaling targets for critical pitches, gear-ratios, and cell height; defining a set of patterning solutions, required RET restrictions, and resulting patterning cost; compiling physical design objectives to achieve power, performance, and area scaling; developing a set of standard cell logic cell architectures; and finally assessing achievable cell-level as well as macro-level scaling.

Rectilinear block placement using sequence-pair

Abstract: With the recent advent of deep sub-micron technology and new packaging schemes such as Multi-Chip Modules(MCMs), integrated circuit components are often not rectangular. Most existing block placement approaches, however, only deal with rectangular blocks, resulting in inefficient area utilization. New approaches which can handle arbitrarily shaped blocks are essential to achieve high performance design. In this paper, we present an approach extending the sequence-pair approach for rectangular block placement to arbitrarily sized and shaped rectilinear blocks. Experimental results show that our algorithm achieves results with excellent area utilization.

Method and apparatus for recording and viewing error data generated from a computer simulation of an integrated circuit

Abstract: A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simulation results are identified and recorded along with the identified errors. Recorded error-specific data and transaction-specific data are then utilized to graphically display the simulation results such that individual transactions identified within the simulation results are graphically distinct and such that errors occurring during a transaction are visually identified with the transaction. Recording and displaying error information and raising the level of abstraction of simulation results from cycles and signals to transactions enables easier simulation analysis and debugging.

A single-instance incremental SAT formulation of proof- and counterexample-based abstraction

Abstract: This paper presents an efficient, combined formulation of two widely used abstraction methods for bit-level verification: counterexample-based abstraction (CBA) and proof-based abstraction (PBA). Unlike previous work, this new method is formulated as a single, incremental SAT-problem, interleaving CBA and PBA to develop the abstraction in a bottom-up fashion. It is argued that the new method is simpler conceptually and implementation-wise than previous approaches. As an added bonus, proof-logging is not required for the PBA part, which allows for a wider set of SAT-solvers to be used.