Cadence Design Systems

About: Cadence Design Systems is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Circuit design & Routing (electronic design automation). The organization has 3139 authors who have published 3745 publications receiving 66410 citations. The organization is also known as: Cadence Design Systems, Inc.

An efficient approach to transmission line simulation using measured or tabulated S-parameter data

Abstract: In this paper we describe an algorithm for efficient circuit-level simulation of transmission lines which can be specified by tables of frequency-dependent scattering parameters. The approach uses a forced stable section-by-section l2 minimization approach to construct a high order rational function approximation to the frequency domain data, and then applies guaranteed stable balanced realization techniques to reduce the order of the rational function. The rational function is then incorporated in a circuit simulator using fast recursive convolution. An example of a transmission line with skin-effect is examined to both demonstrate the effectiveness of the approach and to show its generality.

Method, System, and Computer Program Product for Implementing a Model Exchange Framework

Abstract: Disclosed are a method, a system, and a computer program products for implementing model exchange in a system design. In various embodiments, the method or system receives a model exchange request from a client where model exchange request comprises a first synchronization record which comprises a delta of both a program aspect and a data aspect between a system design on the client and a system design on the server, implements the first model exchange request by processing the first model exchange, generates a second synchronization record in response to the first model exchange, transmitting the second synchronization record to the first client by using a fusion technology, and displaying a result of implementing the first model exchange request or storing the result in a tangible computer readable medium.

A method for modeling bidirectional or multiplicatively driven signal paths in a system to achieve a general purpose statically scheduled simulator

Abstract: A method is disclosed whereby systems having bidirectional and/or multiplicatively driven data paths are statically scheduled for simulation. The method flattens the netlist to convert bidirectional data flow paths into unidirectional, multiplicatively driven data paths. All drivers connected to multiplicatively driven data paths (or nets) are isolated from the net using a bus resolution block. The bus resolution block implements a resolution function which permits the system to be statically scheduled for simulation. Simulation speed is increased substantially thereby.

Method and system for false path analysis

Abstract: Disclosed are methods and systems for performing false path analysis. In one approach, the methods and systems identify a set of zero or more false paths based upon both implementation-specific design data and non-implementation-specific design data. In some approaches, disclosed are methods and systems for performing automated gate-level static timing false path analysis, identification, constraint generation, and/or verification using architectural information. Static timing paths at the gate-level can be linked to the architectural information via mapping techniques found in equivalence checking (EC). The gate level static timing paths can be analyzed in the context of the architectural information to identify false paths.

More practical bounded-skew clock routing

Abstract: Academic clock routing research results has often hadlimited impact on industry practice, since such practical considerationsas hierarchical buffering, rise-time and overshoot constraints,obstacle- and legal location-checking, varying layer parasitics andcongestion, and even the underlying design flow are often ignored.This paper explores directions in which traditional formulationscan be extended so that the resulting algorithms are more usefulin production design environments. Specifically, the following issuesare addressed: (i) clock routing for varying layer parasiticswith nonzero via parasitics; (ii) obstacle-avoidance clock routing;(iii) a new topology design rule for prescribed-delay clock routing;and (iv) predictive modeling of the clock routing itself. Wedevelop new theoretical analyses and heuristics, and present experimentalresults that validate our new approaches.