Journal ArticleDOI
A CMOS time-to-digital converter with better than 10 ps single-shot precision
TLDR
A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.Abstract:
A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.read more
Citations
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Journal ArticleDOI
A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
Minjae Lee,Asad A. Abidi +1 more
TL;DR: A new coarse-fine TDC architecture is proposed by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process, which will improve the linearity further.
Journal ArticleDOI
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping.
Journal ArticleDOI
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power
Davide Tasca,Marco Zanuso,Giovanni Marzin,Salvatore Levantino,Carlo Samori,Andrea L. Lacaita +5 more
TL;DR: This paper introduces a fractional-N PLL based on a 1b TDC, achieving jitter of 560fsrms (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worst-case of fractional spur falling within the PLL bandwidth.
Journal ArticleDOI
CMOS Imager With 1024 SPADs and TDCs for Single-Photon Timing and 3-D Time-of-Flight
Federica Villa,Rudi Lussana,Danilo Bronzi,Simone Tisa,Alberto Tosi,Franco Zappa,Alberto Dalla Mora,Davide Contini,Daniel Durini,Sascha Weyers,Werner Brockherde +10 more
TL;DR: In this article, the authors present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities.
Journal ArticleDOI
A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology
M. Gersbach,Yuki Maruyama,Rahmadi Trimananda,Matthew W. Fishburn,David Stoppa,Justin Richardson,Richard Walker,Robert Henderson,Edoardo Charbon +8 more
TL;DR: The target application for this sensor is time-resolved imaging, in particular fluorescence lifetime imaging microscopy and 3D imaging, and the characterization shows the suitability of the proposed sensor technology for these applications.
References
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Journal ArticleDOI
The use of stabilized CMOS delay lines for the digitization of short time intervals
Timo Rahkonen,Juha Kostamovaara +1 more
TL;DR: In this paper, the basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed, and the accuracy of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated.
Journal ArticleDOI
Digital Time Intervalometer
TL;DR: In this article, a digital time intervalometer was developed for measuring time intervals of 1 msec or less with a time resolution of ∼200 psec, where the start signal can be delayed from 50 nsec to the full range of ∼1 msec.
Journal ArticleDOI
A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications
B.K. Swann,Benjamin J. Blalock,L.G. Clonts,David M. Binkley,J.M. Rochelle,E. Breeding,K.M. Baldwin +6 more
TL;DR: The design is believed to be the first fully integrated CMOS subnanosecond time-to-digital TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.
Journal ArticleDOI
Review of Sub-Nanosecond Time-Interval Measurements
TL;DR: A review of time-interval measurements in the sub-nanosecond regime is presented and various methods are compared as to their precision, stability, resolution, and other essential parameters.
Proceedings ArticleDOI
A flexible multi-channel high-resolution time-to-digital converter ASIC
TL;DR: In this paper, a data driven multi-channel TDC circuit with programmable resolution (spl sim/25 ps-800 ps binning) and a dynamic range of 102.4 /spl mu/s has been implemented in a 0.25 /spl µ/m CMOS technology.
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