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Proceedings ArticleDOI

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops

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TLDR
A fabricated nonvolatile processor based on ferroelectric flip-flops can operate continuously even under power failures occurring at 20 KHz and will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.
Abstract
Nonvolatile processors offer a number of desirable properties including instant on/off, zero standby power and resilience to power failures. This paper presents a fabricated nonvolatile processor based on ferroelectric flip-flops. These flipflops are used in a distributed fashion and are able to maintain system states without any power supply indefinitely. An efficient controller is employed to achieve parallel reads and writes to the flip-flops. A reconfigurable voltage detection system is designed for automatic system backup during power failures. Measurement results show that this nonvolatile processor can operate continuously even under power failures occurring at 20 KHz. It can backup system states within 7μs and restore them within 3 μs. Such capabilities will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.

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Citations
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Proceedings ArticleDOI

Design exploration of inrush current aware controller for nonvolatile processor

TL;DR: This paper proposes a distributed backup control architecture for nonvolatile processors to cope with the inrush current problem and devise corresponding algorithms to accelerate backup operations under given maximum tolerable current constraints.
Patent

Nonvolatile logic array with built-in test drivers

TL;DR: In this article, a system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells, each of the bit cells is configured to store a bit of data.
Proceedings ArticleDOI

Highly Reliable Non-Volatile Logic Circuit Technology and Its Application

TL;DR: A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI and the use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention under less than 1.5V operation.
Proceedings ArticleDOI

Ferroelectric HfO2 and Its Impact on the Memory Landscape

TL;DR: The work illustrates that due to the fact that HfO2 has been established as the de facto standard high-k material in industry, the discovered ferroelectric properties in that same material might impact the existing memory landscape as a whole.
Proceedings ArticleDOI

Full-adder circuit design based on all-spin logic device

TL;DR: This paper proposes a one-bit full-adder and a multi-bits adder circuits relying on ASL devices and evaluates the performances of the circuits with transient simulation using a compact model ofASL devices developed in Cadence.
References
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Proceedings ArticleDOI

A compression-based area-efficient recovery architecture for nonvolatile processors

TL;DR: A compare and compress recovery architecture, consisting of a parallel run-length codec (PRLC) and a state table logic, to reduce the area of nonvolatile registers and a heuristic vector selecting algorithm, which can provide over 42% better register number reduction than other vector selecting approaches.
Proceedings ArticleDOI

A non-volatile microcontroller with integrated floating-gate transistors

TL;DR: Experiments indicate that the proposed architecture has minimal impact on normal operation while enabling all processor state to be preserved across an unexpected power interruption, and careful system-level optimizations to hide expensive non-volatile operations are evaluated.
Proceedings ArticleDOI

A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications

TL;DR: A novel compare-and-write ferroelectric nonvolatile flip-flop is developed, which can be used in the checkpoint processor for energy-harvesting applications and can make the processornonvolatile, secure and instant recoverable from power failures.
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