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Proceedings ArticleDOI

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops

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TLDR
A fabricated nonvolatile processor based on ferroelectric flip-flops can operate continuously even under power failures occurring at 20 KHz and will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.
Abstract
Nonvolatile processors offer a number of desirable properties including instant on/off, zero standby power and resilience to power failures. This paper presents a fabricated nonvolatile processor based on ferroelectric flip-flops. These flipflops are used in a distributed fashion and are able to maintain system states without any power supply indefinitely. An efficient controller is employed to achieve parallel reads and writes to the flip-flops. A reconfigurable voltage detection system is designed for automatic system backup during power failures. Measurement results show that this nonvolatile processor can operate continuously even under power failures occurring at 20 KHz. It can backup system states within 7μs and restore them within 3 μs. Such capabilities will provide a new level of support to chip-level fine-grained power management and energy harvesting applications.

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Citations
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Q-learning based backup for energy harvesting powered embedded systems

TL;DR: This work proposes a Q-learning based backup strategy to achieve maximal forward progress in energy harvesting powered intermittent embedded systems and shows results that show an average of 307.4% and 43.
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Leveraging nonvolatility for architecture design with emerging NVM

TL;DR: The potential benefit by leveraging nonvolatility for architecture design is pointed out and two case studies are described, which support persistency in NVM based main memory.
Proceedings ArticleDOI

Register allocation for hybrid register architecture in nonvolatile processors

TL;DR: This paper proposes a critical-data overflow aware register allocation (CORA), which efficiently reduces the possibility of critical data spilling and backup errors and provides a partial replacement based hybrid register architecture to significantly abate above problems.
Journal ArticleDOI

Image-Content-Aware I/O Optimization for Mobile Virtualization

TL;DR: This paper proposes a novel I/O optimization techniqueto identify the metadata of a guest file system which is stored in a VM (Virtual Machine) image file and frequently updated, and stores these metadata in a small additional NVM (Non-Volatile Memory) which is faster and more endurable to greatly improve flash memory's performance and lifetime.
Patent

Nonvolatile Logic Array And Power Domain Segmentation In Processing Device

TL;DR: In this paper, a computing device includes a first set of nonvolatile logic element arrays associated with a first function and a second set of NLLE arrays associated to a second function.
References
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Proceedings ArticleDOI

A compression-based area-efficient recovery architecture for nonvolatile processors

TL;DR: A compare and compress recovery architecture, consisting of a parallel run-length codec (PRLC) and a state table logic, to reduce the area of nonvolatile registers and a heuristic vector selecting algorithm, which can provide over 42% better register number reduction than other vector selecting approaches.
Proceedings ArticleDOI

A non-volatile microcontroller with integrated floating-gate transistors

TL;DR: Experiments indicate that the proposed architecture has minimal impact on normal operation while enabling all processor state to be preserved across an unexpected power interruption, and careful system-level optimizations to hide expensive non-volatile operations are evaluated.
Proceedings ArticleDOI

A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications

TL;DR: A novel compare-and-write ferroelectric nonvolatile flip-flop is developed, which can be used in the checkpoint processor for energy-harvesting applications and can make the processornonvolatile, secure and instant recoverable from power failures.
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