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A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAM

TLDR
In this paper, a built-in structure allows collecting statistical data related to the OxRRAM memory array (ON/OFF resistance distributions) for reliability assessment of the technology, which is a key parameter to determine the overall performance.
Abstract
Resistive Random Access Memory (RRAM) is a form of nonvolatile storage that operates by changing the resistance of a specially formulated solid dielectric material [1] . Among RRAMs, oxide-based Resistive RAMs (so-called OxRRAMs) are promising candidates due their compatibility with CMOS processes and high ON/OFF resistance ratio. Common problems with OxRRAM are related to high variability in operating conditions and low yield. OxRRAM variability mainly impact ON/OFF resistance ratio. This ratio is a key parameter to determine the overall performance of an OxRRAM memory. In this context, the presented built-in structure allows collecting statistical data related to the OxRRAM memory array (ON/OFF resistance distributions) for reliability assessment of the technology.

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Citations
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Journal ArticleDOI

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing

TL;DR: A novel unary coding of synaptic weights is proposed to overcome the resistance variations of MLCs and achieve reliable ReRAM-based neuromorphic computing.
Proceedings ArticleDOI

Simulation of RRAM memory circuits, a Verilog-A compact modeling approach

TL;DR: Three different compact models for resistive RAM are introduced and the role of the conductive filaments ohmic resistance is introduced for different filament shapes, affecting the voltage at the gap between the filament tip and the electrode, and therefore the device hopping current.
Journal ArticleDOI

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers

TL;DR: Combining RRAM technology and architectural enhancements, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 57 percent and Delay-Power Product by 38 percent, as compared to a SRAM-basedFPGA exploiting a classical architecture.
Journal ArticleDOI

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

TL;DR: A synthesizable Verilog generator for both SRAM-based and RRAM-based FPGAs is developed and a full FPGA fabric is considered, including core logic, configuring peripherals, and I/Os, which is more realistic than analytical models and is more capable of trading-off energy and quality than the SRam-based counterparts.

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang
TL;DR: This thesis presents high-performance and low-power RRAM-based FPGAs from transistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools.
References
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Journal ArticleDOI

Reproducible resistance switching in polycrystalline NiO films

TL;DR: Negative resistance behavior and reproducible resistance switching were found in polycrystalline NiO films deposited by dc magnetron reactive sputtering methods in this paper, where the negative resistance and the switching mechanism could be described by electron conduction related to metallic nickel defect states existing in deep levels and by small polaron hole hopping conduction.
Journal ArticleDOI

Switching properties of thin Nio films

TL;DR: In this paper, the authors describe a two-terminal solid-state switch made from a thin film of nickel oxide, which has a typical OFF resistance of 10−20 MΩ and a typical ON resistance of 100−200 Ω.
Proceedings ArticleDOI

Variability of resistive switching memories and its impact on crossbar array performance

TL;DR: In this paper, the variability of key RRAM parameters with the focus on the resistance variation is discussed, and the dependence of resistance variation on operation conditions is analyzed, using Cu 2 O-based RRAM as an example.
Journal ArticleDOI

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

TL;DR: A theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL) is presented and special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs.
Proceedings ArticleDOI

Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO 2 -RRAM integrated in a 65nm CMOS technology

TL;DR: In this article, the effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance State (HRS) are explored, and the conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model.
Related Papers (5)
Frequently Asked Questions (18)
Q1. What are the contributions mentioned in the paper "A built-in self-test structure (bist) for resistive rams characterization: application to bipolar oxrram" ?

In this paper, the authors proposed a built-in self-test structure ( BIST ) to evaluate OxRRAM variability at a circuit level. 

Electroforming stage corresponds to a voltage-induced resistance switching from an initial very high resistance state (virgin state) to a conductive state. 

OxRRAM presents a lot of interesting features like high integration density, high-speed operations (write/erase/read) and satisfactory reliability performances in terms of retention and cycling. 

The proposed OxRRAM modeling approach relies on electric field-induced creation/destruction of oxygen vacancies within the switching layer. 

As variability in OxRRAMs presents a major challenge for fabrication process and design engineers, the BIST structure can be used to quickly evaluate cell variability impact on the ON/OFF resistance ratio of a whole memory array. 

For instance, for mobile applications containing OxRRAMs, the trend would be to reduce the cell consumption without compromising reliability. 

For each VREAD value, 100 Monte Carlo simulations are performed after a SET and a RESET operation to extract the sense amplifier VIN distributions. 

In this study, a large number of Monte Carlo simulations are performed to provide the statistic needed to characterize variability and its impact on the circuit. 

Ox ererr dtdr ⋅ ⋅⋅+− ⋅ ⋅⋅−− ⋅⋅−⋅⋅−= α β αβ ReRe 1010max (1)where βRedOx is the nominal oxide reduction rate, Ea is the activation energy, αred and αox are the transfer coefficients (ranging between 0 and 1), kb is the Boltzmann constant, T is the temperature and Vcell the voltage across the cell. 

Resistive switching in an OxRRAM element corresponds to an abrupt change between a High Resistance State (HRS or OFF state) and a Low Resistance State (LRS or ON state). 

To take into account IOX trap assisted current (PooleFrenkel, Schottky emission, Space Charge Limited Current (SCLC)), a power law between the cell current and the applied bias is considered with two parameters AHRS and βHRS. 

In its simplest form, resistive memory element relies on a Metal/Insulator/Metal (MIM) stack that can be easily integrated into the Back-End Of Line (BEOL), paving the way for 3D technology. 

The transmission gates of the voltage source are controlled by the shift register presented in Fig. 4b, which shifts a “1” and has all its other bits set to “0”. 

In the case of bipolar switching, addressed in this paper, bipolar voltage sweeps are required to switchthe memory element (Fig. 1). 

8. Therefore, the modified sense amplifier structure can be used as a powerful tool to track any resistance variations but also to characterize the memory array variability. 

the total current flowing through the cell is:OXCFCell III += (4)ICF is the main contributor to LRS current (ILRS) and IOX is the main contributor to HRS current (IHRS). 

Various mechanisms may explain the resistance change (oxygen vacancy migration [4], oxidation-reduction processes, thermal diffusion…). 

the total current inthe OxRRAM includes two components, i.e. one is related to the conductivespecies (IFC) and the other to the conduction through the oxide (IOX).( )( )OXCFOXCFCF x Cell CF rrL V The authorσπσσπ ⋅⋅+−⋅⋅⋅= 2 max 2 (2)HRSxCell CellHRSOX LV SAIβ ⋅= (3)where Lx is the oxide thickness, SCell is the total area of the device, σOx the oxidationrate and σCF the reduction rate.