Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
A low-power 4K point FFT processor for CMMB OFDM receiver system
TL;DR: This paper presents a 4096-point FFT processor for CMMB receiver system, in which dual-path pipelined shared memory architecture is employed, with a data reordering for receiver, an elaborate memory configuration scheme, and single-port SRAM can be adopted without degrading throughput rate.
Proceedings ArticleDOI
Design of parallel FFT architecture using Cooley Tukey algorithm
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Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications
Song-Nien Tang,Yuan-Ho Chen +1 more
TL;DR: The proposed design uses a mixed-radix, mixed-multipath delay-feedback (MRM2DF) structure, which enables 4/5/6-stream 64/128-point FFT, and allows the effective usage of guard intervals (GI) in conjunction with a novel resource-sharing scheme to improve area efficiency.
Proceedings ArticleDOI
Fast fourier transform based ip traffic classification system for SIPTO at H(e)NB
TL;DR: Results show that the proposed fast fourier transform based IP traffic classification system for SIPTO at H(e)NB outperforms existing methods by offering about 3%-6% improvement in classification accuracy with about 7% time.
References
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.