Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
Energy-optimized high performance FFT processor
TL;DR: An ultra low energy FFT processor suitable for sensor applications that achieves 9.25x higher energy efficiency than state-of-the-art FFT processors and high throughput relative to past subthreshold circuit implementations is proposed.
Proceedings ArticleDOI
High-Throughput 64K-point FFT Processor for THz Imaging Radar System
TL;DR: This paper implements a 4-parallel 64K-point FFT hardware architecture based on 2-epoch FFT algorithm and reduces a large number of storages for twiddle factor coefficients, so that the area of ROM can be reduced.
Proceedings ArticleDOI
Transport Triggered Architecture Processor for Mixed-Radix FFT
TL;DR: The paper describes an FFT implementation supporting power-of-two FFTs with the aid of mixed- radix algorithm based on radix-4 andRadix-2 computations, which is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.
Journal ArticleDOI
Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage
TL;DR: This paper describes a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors.
Proceedings ArticleDOI
Pixel-and-column pipeline architecture for FFT-based image processor
TL;DR: In this article, a pixel-and-column pipeline architecture is proposed for phase correlation and Fourier-Mellin transform based image-processing algorithms, and an LSI that provides those algorithms at the real-time response is designed based on the architecture.
References
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.