Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
Reads0
Chats0
TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
More filters
Dissertation
Architecture de circuit intégré reconfigurable, très haut débit et basse consommation pour le traitement numérique de l'OFDM avancé
TL;DR: In this article, the authors propose an architecture a base of memoires utilisant un multiplexage temporel des operations sur une matrice de calcul a gros grain optimisee for le traitement de la transformee de Fourier rapide and le filtrage polyphase.
Proceedings ArticleDOI
A low power MMSE receiver architecture for multi-carrier CDMA
TL;DR: Simulations using data consistent with typical performance of a multi-carrier CDMA receiver indicate that the block based approach can produce a power reduction of around 50%.
Journal ArticleDOI
An Ultra-long FFT Architecture Implemented in a Reconfigurable Application Specified Processor
TL;DR: An efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit is presented and an efficient 2-epoch FFT solution is realized.
Journal ArticleDOI
Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems
Amjadha. A,E. Konguvel,J. Raja +2 more
TL;DR: An efficient implementation of FFT/IFFT processor for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length is presented and shows the advantages of the proposed scheme in terms of area and power consumption.
Proceedings ArticleDOI
High speed FFT processor design using radix − 4 pipelined architecture
Swapnil Badar,D.R. Dandekar +1 more
TL;DR: High speed FFT processor with pipelined architecture which is efficient in terms of latency, with using fastest processing elements using two different types of fixed point multipliers based on Vedic mathematics.
References
More filters
Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Book
Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
Book
Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.