Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Journal ArticleDOI
Low-power and high-throughput 128-point feedforward FFT processor
TL;DR: This proposed FFT processor is designed using Verilog and implemented using 180 nm CMOS Technology with supply voltage of 1.8v and shows significant reduction in power consumption in comparison with existing design and increasing throughput with area trade off.
Proceedings ArticleDOI
Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture
Jakub Zadnik,Jarmo Takala +1 more
TL;DR: A low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited, which is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations.
Journal ArticleDOI
On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture
TL;DR: In this article, the authors presented an on-chip implementation of pipeline digit slicing multiplier-less butterfly for FFT structure, in order to reduce computation complexity in butterfly, digit-slicing multiplier less single constant technique was utilized in the critical path of Radix-2 Decimation in time (DIT) FFT.
Journal ArticleDOI
Efficient FFT network testing and diagnosis schemes
Jin-Fu Li,Cheng-Wen Wu +1 more
TL;DR: A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented and reduces the diagnosis complexity from O(N) to O(1).
Journal ArticleDOI
A New Multichannel Parallel Real-time FFT Algorithm for a Solar Radio Observation System Based on FPGA
TL;DR: A multichannel parallel FFT algorithm named the MPR-FFT, which can greatly reduce FPGA resource occupation while increasing the real-time processing speed and reduced the computational resources to a large extent.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Book
Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
Book
Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.