Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications
TL;DR: This paper proposes two novel parallel-pipelined FFT architectures, based on multiplier-less implementation, targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver, with advantages of high throughput and high power efficiency.
Journal ArticleDOI
An Area Efficient 1024-Point Low Power Radix-2 2 FFT Processor With Feed-Forward Multiple Delay Commutators
Ngoc Le Ba,Tony Tae-Hyoung Kim +1 more
TL;DR: An improved input scheduling algorithm based upon memory is proposed to eliminate energy required to shift data along the delay lines and be more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths.
Journal ArticleDOI
A Spurious-Power Suppression Technique for Multimedia/DSP Applications
Kuan-Hung Chen,Yuan-Sun Chu +1 more
TL;DR: This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes and proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period.
Journal ArticleDOI
Energy-Efficient Signal Processing Using FPGAs
Proceedings ArticleDOI
Energy efficient parameterized FFT architecture
TL;DR: A parameterized FFT architecture is proposed to identify the design trade-offs in achieving energy efficiency, and designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.