Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Journal ArticleDOI
FFT Traffic Classification-Based Dynamic Selected IP Traffic Offload Mechanism for LTE HeNB Networks
TL;DR: Simulation results show that FFTTCS can realize on-line traffic classification with similar precisions but only using less than 10 % of the time needed by existing methods.
Proceedings ArticleDOI
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters
TL;DR: In this article, the authors compare buffer-less and buffered FFT accelerators for complex data with 8/16/32-bit real and imaginary parts and show that bufferless accelerators can be made as fast as buffered accelerators at only 0.26× the area cost.
Book ChapterDOI
Low-power, high-performance TTA processor for 1024-point fast fourier transform
TL;DR: In this paper, a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT) processor, which consumes only 1.55 μJ of energy.
Journal ArticleDOI
Design Space Exploration of 1-D FFT Processor
Shaohan Liu,Dake Liu +1 more
TL;DR: A design space exploration methodology of 1-D FFT processor is proposed to find the best hardware architecture in a quantitative way during early design and has better normalized throughput per area unit and normalized FFTs per energy unit than the state of the art available designs.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
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Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.