Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
LaFFT: Length-Aware FFT Based Fingerprinting for Encrypted Network Traffic Classification
TL;DR: Length-aware FFT (LaFFT) fingerprinting is developed to identify different encrypted application traffic with packet length sequences to generate the frequency domain vectors as LaFFT features and the linear inseparability and the front superiority of LaffT fingerprinting are demonstrated.
Journal ArticleDOI
Low power reconfigurable FP-FFT core with an array of folded DA butterflies
TL;DR: A variable length (32 ~ 2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers.
Proceedings ArticleDOI
Scalable interconnection networks for partial column array processor architectures
TL;DR: These networks realize the data reordering found in constant geometry radix-2/sup r/ algorithms, which exist, e.g., for discrete Fourier, sine, cosine, and Hartley transforms.
Proceedings ArticleDOI
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
TL;DR: A single-chip 512-point FFT processor is presented, based on the cached-memory architecture with the resource saving multi-datapath radix-2/sup 2/ computation element, and the 2-stage CMA, including a pair of single-port SRAMs is introduced to speedup the execution time of the2-dimensional FFTs.
Proceedings ArticleDOI
A Low-Cost 256-Point FFT Processor for Portable Speech and Audio Applications
TL;DR: Circuit simulation and implementation results show that the proposed 256-point FFT processor is well suited for portable speech and audio applications.
References
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Discrete-Time Signal Processing
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.