Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems
TL;DR: This paper designs and implements a programmable 64/spl sim/2048-point FFT/IFFT processor and implements the Processing Element by using CORDIC algorithm to replace the multiplier-based PE, and proposes /spl pi//4-prerotation and modified EEAS-CORDIC VLSI architecture to reduce the iteration number and quantization noise.
Proceedings ArticleDOI
A Block Scaling FFT/IFFT Processor for WiMAX Applications
Yuan Chen,Yu-Wei Lin,Chen-Yi Lee +2 more
TL;DR: A novel block scaling method and a new ping-pong cache-memory architecture are proposed to reduce the power consumption and hardware cost and by proper scheduling of the two data streams, the proposed design achieves better hardware utilization.
Proceedings ArticleDOI
A high throughput FFT processor with no multipliers
TL;DR: Replacing the sine and cosine twiddle factors in the conventional FFT architecture by non-iterative CORDIC micro-rotations which allow substantial (~ 50%) reduction in read-only memory (ROM) table size, and total removal of complex multipliers.
Journal ArticleDOI
An Energy-Efficient Partial FFT Processor for the OFDMA Communication System
TL;DR: A partial cached fast Fourier transform (FFT) processor that accounts for the distribution of allocated resources to the users of the OFDMA system is designed and a constellation- and power-aware twiddle-factor multiplier for the variable FFT length and modulation order is designed.
Journal ArticleDOI
FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data
Jung Sub Kim,Chi-Li Yu,Lanping Deng,Srinidhi Kestur,Vijaykrishnan Narayanan,Chaitali Chakrabarti +5 more
TL;DR: This paper proposes an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm that is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.
References
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
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Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.