Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Journal Article
Parallel-computing Approach for FFT Implementation on Digital Signal Processor (DSP)
Yi-Pin Hsu,Shin-Yu Lin +1 more
TL;DR: A parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference is proposed.
Proceedings ArticleDOI
A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN
TL;DR: By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100% and the hardware complexity is significantly reduced.
Journal ArticleDOI
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design
TL;DR: Embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design based on the observation that the FFT processor has regular and predictable memory access patterns and it can be efficiently exploited for memory customization using eDRAM.
Proceedings ArticleDOI
Energy performance of FPGAs on PERFECT suite kernels
Sanmukh R. Kuppannagari,Ren Chen,Andrea Sanny,Shreyas G. Singapura,Geoffrey Phi C. Tran,Shijie Zhou,Yusong Hu,Stephen P. Crago,Viktor K. Prasanna +8 more
TL;DR: This work designs parameterized architectures for six kernels selected from the PERFECT benchmark suite, and develops optimizations targeted at reducing memory and communication energy dissipation on FPGAs.
Journal ArticleDOI
Fast: FFT ASIC automated synthesis
TL;DR: An automated design method for the synthesis of a high-throughput fast Fourier transform (FFT) ASIC is presented, applicable to any power-of-two FFT sizes, resulting in an area-time product nearly 30% lower than previous works following automatic-design methodologies.
References
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Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.