Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Journal ArticleDOI
FPGA implementations of fast Fourier transforms for real-time signal and image processing
TL;DR: The design and realisation of a high level framework for the implementation of 1-D and 2-D FFTs for real-time applications and an FPGA-based parametrisable environment based on 2- D FFT is presented as a solution for frequency-domain image filtering application.
Journal ArticleDOI
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications
TL;DR: A novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed and a multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is presented.
Journal ArticleDOI
New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy
B.G. Jo,Myung Hoon Sunwoo +1 more
TL;DR: A new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy that can reduce hardware complexity and computation cycles compared with existing FFT processors is proposed.
Book ChapterDOI
Mode Coupling and its Impact on Spatially Multiplexed Systems
Keang-Po Ho,Joseph M. Kahn +1 more
TL;DR: This chapter provides an in-depth description of mode coupling, including its physical origins, its effect on modal dispersion (MD) and mode-dependent loss or gain (MDL), and the resulting impact on system performance and implementation complexity.
Journal ArticleDOI
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
TL;DR: A design methodology for power and area minimization of flexible FFT processors based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables is presented.
References
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Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
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Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.