Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Journal ArticleDOI
Design and study of system on chip design for signal processing applications in terms of energy and area
TL;DR: In this paper, the authors quantify the cost of providing flexibility in terms of energy consumption and silicon area and find that the critical architectural parameters are the amount of flexibility, the granularity of the architecture in providing this flexibility and the number of parallelism.
Dissertation
Removing Redundancies of Fast Fourier Transform Computations
TL;DR: This paper aims to demonstrate the power of data analytics in the rapidly changing environment to provide real-time information about the physical environment and provide insights into the design and engineering of smart devices.
Proceedings ArticleDOI
Low-Power High-Speed Radix-2 DIT FFT Suitable for AAC/DRA Audio Decoding
TL;DR: An implementation of low-power, high-speed radix-2 DIT (Decimation-in-time) FFT suitable for AAC/DRA audio decoding is presented, and two methods are adopted: adding cache to ROM (ROM-cache) and proposing a new butterfly (AI-Butterfly).
Dissertation
A comparison of FFT processor designs
TL;DR: Four new ASIC designs are compared to the existing one, in search of a better solution, and an approach that uses the minimal amount of memory (SDF), and one that uses more memory for faster calculation (MDC) are implemented for both radix-2 andRadix-4 designs.
Proceedings ArticleDOI
Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
TL;DR: In this article, the authors proposed an optimal constant multiplication arithmetic design to multiply a fixed point input selectively by one of the several present twiddle factor constants, which can be found as significant improvement over Radix 22 DIF SDF FFT processor and can enable in solving problems that affect the most high-speed wireless communication systems capability in FFT and possesses huge potentials for future related works and research areas.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.