Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Proceedings ArticleDOI
A hierarchical design of an application-specific instruction set processor for high-throughput FFT
Xuan Guan,Yunsi Fei,Hai Lin +2 more
TL;DR: A novel hierarchical design of an application-specific instruction set processor (ASIP) tailored for Fast Fourier Transformation (FFT), a kernel data transformation task in digital communication systems, to meet the stringent requirements on throughput and flexibility is presented.
Proceedings ArticleDOI
A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications
TL;DR: This paper investigates the energy efficacy of the asynchronous (async) logic over its synchronous (sync) counterpart in a 128-point FFT/IFFT processor for low voltage energy-critical medium-to-low speed applications including hearing aids.
Proceedings ArticleDOI
High-speed assembly FFT implementation with memory reference reduction on DSP processors
TL;DR: This paper proposes a hand-coded assembly implementation for the radix-2 DIF FFT algorithm with the twiddle-factor-based butterfly grouping method on a TI TMS320C64/spl times/ DSP that is 8 times faster than the C implementation and slightly slower than the TI assembly benchmark while requiring only 50% of memory references due to twiddle factors.
Book ChapterDOI
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths
TL;DR: In this article, the use of low power techniques applied to FIR filter and FFT dedicated datapath architectures is discussed, where new low power arithmetic operators are used as basic modules and a new algorithm for the partitioning and ordering of the coefficients is presented.
Proceedings ArticleDOI
Design of Low Power Mixed Radix FFT Processor for MIMO OFDM Systems
M. P. Chitra,S. K. Srivatsa +1 more
TL;DR: The proposed FFT Processor not only supports the operation of FFT in 128 point and 64 point but can also provide different throughput rates for 1-4 simultaneous data sequence to meet IEEE 802.11n requirements.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
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Discrete-Time Signal Processing
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
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Theory and application of digital signal processing
TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.