Journal ArticleDOI
A low-power, high-performance, 1024-point FFT processor
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TLDR
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor, which has been fabricated in a standard 0.7 /spl mu/m CMOS process and is fully functional on first-pass silicon.Abstract:
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.read more
Citations
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Dissertation
Low-Power Architectures for Signal Processing and Classification Systems
TL;DR: This dissertation presents a meta-modelling system that automates the very labor-intensive and therefore time-heavy and therefore expensive and expensive process of systematically cataloging and cataloging individual neurons in the brain.
Journal ArticleDOI
A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition
TL;DR: A novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT.
Book ChapterDOI
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm
TL;DR: This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture, which presents a memory management scheme that avoids memory contention throughout the pipeline stages.
Proceedings ArticleDOI
An interconnect-driven design of a DFT processor
TL;DR: A new interconnect-driven DFT implementation is proposed in this paper to reduce the power consumption and the possibility to calculate a spectrum of any length, not only a power of two, and to have an irregular frequency step between channels.
Proceedings ArticleDOI
An efficient FFT/IFFT architecture for wireless communication
TL;DR: This paper presents an efficient implementation of a reconfigurable FFT/IFFT processor for wireless applications that adopts a single-path delay feedback style as to eliminate the read-only memories which are used to store the twiddle factors.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.