Journal ArticleDOI
Analog performance investigation of dual electrode based doping-less tunnel FET
TLDR
In this paper, dual electrode doping-less TFET (DEDLTFET) was proposed to enhance the ON state current and Analog performances, where electrodes on top and bottom of source and drain are considered to enhance ON state currents and analog performances.Abstract:
In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron's and hole's clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance $$(\hbox {g}_\mathrm{m})$$(gm), transconductance to drain current ratio $$(\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})$$(gm/ID), output-conductance (g$$_{d})$$d), output resistance $$(\hbox {r}_\mathrm{d})$$(rd), early voltage $$(\hbox {V}_\mathrm{EA})$$(VEA), intrinsic gain $$(\hbox {A}_\mathrm{V})$$(AV), total gate capacitance $$(\hbox {C}_\mathrm{gg})$$(Cgg) and unity gain frequency $$(\hbox {f}_\mathrm{T})$$(fT). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.read more
Citations
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Journal ArticleDOI
Design and Performance Analysis of Dielectrically Modulated Doping-Less Tunnel FET-Based Label Free Biosensor
TL;DR: In this article, a charge plasma-based doping less double gated tunnel FET (DLDGTFET)-based biosensor using dielectric modulation with a cavity introduced at the source side for the label free sensing of the biomolecules.
Proceedings Article
Scaling properties of the tunneling field effect transistor (TFET) : Device and circuit
Th. Nirschl,Henzler,J. Fischer,M. Fulde,A. Bargagli-Stoffi,M. Sterkel,J. Sedlmeir,Cory E. Weber,R. Heinrich,U. Schaper,J. Einfeld,R. Neubert,U. Feldmann,Knut Stahrenberg,E. Ruderer,Georg Georgakos,A. Huber,R. Kakoschke,Walter Hansch,Doris Schmitt-Landsiedel +19 more
TL;DR: In this paper, the scaling properties of TFETs were investigated using standard 130 nm, 90 nm, and 65 nm CMOS process flows. But the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET.
Journal ArticleDOI
Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges
Naveen Kumar,Ashish Raman +1 more
TL;DR: In this article, a gate-all-around (GAA) silicon vertical nanowire tunnel field effect transistor (NWTFET) is proposed, and the effects of interface trap charges (ITCs) on dopingless (DL) NW-based device are addressed for the first time.
Journal ArticleDOI
Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET
TL;DR: In this article, the authors have put forward a Silicon based Nanotube structure with dual gate all around configuration, which exhibited superior analog characteristics over its Nanowire counterpart in terms of drive current (ION), electrical criteria, capacitance, unity gain, and transconductance.
Journal ArticleDOI
Design and Performance Optimization of Novel Core–Shell Dopingless GAA-Nanotube TFET With Si 0.5 Ge 0.5 -Based Source
TL;DR: The proposed nanotube structures are optimized to maintain the uniformity of the induced CP within the source/drain regions and enhances the device performance by attaining an average subthreshold slope of 31.38 mV/dec with a higher ON-current.
References
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Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.