Journal ArticleDOI
Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs
Marcelo Antonio Pavanello,Marcelo Antonio Pavanello,Joao Antonio Martino,Joao Antonio Martino,Eddy Simoen,Rita Rooyackers,Nadine Collaert,Cor Claeys +7 more
TLDR
In this paper, a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material is made.Abstract:
This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.read more
Citations
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Journal ArticleDOI
Junctionless Multiple-Gate Transistors for Analog Applications
Rodrigo T. Doria,Marcelo Antonio Pavanello,Renan Trevisoli,M.M. De Souza,Chi-Woo Lee,Isabelle Ferain,Nima Dehdashti Akhavan,Ran Yan,Pedram Razavi,Ran Yu,Abhinav Kranti,Jean-Pierre Colinge +11 more
TL;DR: In this article, the analog properties of nMOS junctionless (JL) multigate transistors are compared with those exhibited by inversion-mode (IM) trigate devices of similar dimensions.
Journal ArticleDOI
Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit
Valeriya Kilchytska,M. K. Md Arshad,Sergej Makovejev,Sarah H. Olsen,Francois Andrieu,Thierry Poiroux,O. Faynot,Jean-Pierre Raskin,Denis Flandre +8 more
TL;DR: UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz.
Journal ArticleDOI
Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation
Rodrigo T. Doria,Antonio Luiz Cerdeira,Joao Antonio Martino,Eddy Simoen,Cor Claeys,Marcelo Antonio Pavanello +5 more
TL;DR: In this article, the harmonic distortion exhibited by unstrained and biaxially strained fin-shaped field effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin.
Proceedings ArticleDOI
Analog operation of junctionless transistors at cryogenic temperatures
Rodrigo T. Doria,Marcelo Antonio Pavanello,Renan Trevisoli,M.M. De Souza,Christopher W. Lee,Isabelle Ferain,N. Dehdashti Akhavan,Ran Yan,Pedram Razavi,Ran Yu,Abhinav Kranti,Jean-Pierre Colinge +11 more
TL;DR: In this paper, the analog behavior of nMOS junctionless transistors in the temperature range of 100 K to 473 K was investigated by experimental results and simulations, and it was shown that g m,max of JL devices present a parabolic-like dependence on temperature.
Journal ArticleDOI
Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
Rodrigo T. Doria,Marcelo Antonio Pavanello,Renan Trevisoli,Michelly de Souza,Chi-Woo Lee,Isabelle Ferain,Nima Dehdashti Akhavan,Ran Yan,Pedram Razavi,Ran Yu,Abhinav Kranti,Jean-Pierre Colinge +11 more
TL;DR: In this paper, a comparative study of the analog performance of junctionless transistors and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion has been performed in the temperature range of 223 K up to 473 K.
References
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Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective
V. Subramanian,Bertrand Parvais,Jonathan Borremans,Abdelkarim Mercha,D. Linten,P. Wambacq,Josine Loo,Morin Dehan,C. Gustin,Nadine Collaert,Stefan Kubicek,R.J.P. Lander,J. Hooker,F. N. Cubaynes,Stéphane Donnay,Malgorzata Jurczak,Guido Groeseneken,Willy Sansen,Stefaan Decoutere +18 more
TL;DR: In this paper, the authors compared the performance of FinFETs and planar bulk MOSFET and found that the latter has better voltage gain without degradation of noise or linearity.
Journal ArticleDOI
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
TL;DR: In this paper, a wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of planar double-gate (DG), triple-gate, Fin-FET, Pi-Gate (PG), and single-gate SOI MOSFETs.
Journal ArticleDOI
FinFET analogue characterization from DC to 110 GHz
Dimitri Lederer,Valeriya Kilchytska,Tamara Rudenko,Nadine Collaert,Denis Flandre,Abhisek Dixit,Abhisek Dixit,K. De Meyer,K. De Meyer,Jean-Pierre Raskin +9 more
TL;DR: In this article, the analogue performance of 50 nm gate length FinFETs is investigated under static and dynamic conditions up to 110 GHz, and it is shown that a non-uniform silicidation of the three-dimensional polysilicon gate can have a strong impact on the device maximum frequency of oscillation (f(max)).
Journal ArticleDOI
Impact of fin width on digital and analog performances of n-FinFETs
V. Subramanian,Abdelkarim Mercha,Bertrand Parvais,Josine Loo,C. Gustin,Morin Dehan,Nadine Collaert,Malgorzata Jurczak,Guido Groeseneken,Willy Sansen,Stefaan Decoutere +10 more
Abstract: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs ( I – V , C – V and 1/ f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/ f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.