Journal ArticleDOI
Efficient Jitter Analysis for a Chain of CMOS Inverters
TLDR
An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.Abstract:
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.read more
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Proceedings ArticleDOI
A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS
TL;DR: This paper presents the design of a 6-bit scalable hybrid flash SAR (successive approximation register) analog-to-digital converter (ADC), which has a scalable architecture because of the usage of an inverter based comparator.
Proceedings ArticleDOI
Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects
TL;DR: This paper presents an efficient method for the estimation of jitter due to power supply noise in a chain-of-inverters including the on-chip-interconnects including the SPICE-based simulations.
Journal ArticleDOI
Device Parameters Based Analytical Modeling of Ground-Bounce Induced Jitter in CMOS Inverters
TL;DR: In this paper , an analytical approach to estimate jitter in CMOS inverters in the presence of ground-bounce noise (GBN) is presented, where the relationship between output and input, considering the effect of ground noise, are derived in terms of device parameters for modeling the timing variations.
Proceedings ArticleDOI
Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network
TL;DR: This paper presents an analysis and estimation of timing error due to the power supply noise for a five-stage CMOS tapered buffer used in the clock distribution network for the application of successive approximation register (SAR).
Journal ArticleDOI
Analytical Modeling of Deterministic Jitter in CMOS Inverters
TL;DR: In this paper , an analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships.
References
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Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Book
Signal and Power Integrity - Simplified
TL;DR: This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design and will be an invaluable resource for getting signal integrity designs right the first time, every time.
Journal ArticleDOI
Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions
TL;DR: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.
Book
Jitter, Noise, and Signal Integrity at High-Speed
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Journal ArticleDOI
Buffer delay change in the presence of power and ground noise
TL;DR: An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics, consistent with short-channel MOSFET behavior, including carrier velocity saturation effects.