Journal ArticleDOI
Efficient Jitter Analysis for a Chain of CMOS Inverters
TLDR
An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.Abstract:
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.read more
Citations
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Journal ArticleDOI
Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.
Proceedings ArticleDOI
An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)
TL;DR: In this paper, an assessment of jitter induced by power and ground (P/G) voltage variations is presented based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers.
Proceedings ArticleDOI
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator
Vijender Kumar Sharma,B. Dinesh Kumar,Muhammed Suhail Illikkal,Jai Narayan Tripathi,Navneet Gupta,Hitesh Shrimali +5 more
TL;DR: The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method and the mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
Proceedings ArticleDOI
Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter
TL;DR: The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained with full SPICE based simulations.
Journal ArticleDOI
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
References
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Proceedings ArticleDOI
Modeling of power supply induced jitter (PSIJ) transfer function at inverter chains
TL;DR: An analytical model of power supply noise induced jitter (PSIJ) at inverter chains is proposed in this paper based on the piecewise linear approximated I-V curve model, closed-form equations of PSIJ transfer function at a single inverter are derived.
Proceedings ArticleDOI
Reducing power-supply and ground noise induced timing jitter in short pulse generation circuits
TL;DR: In this article, the authors present a study of power-supply noise and ground noise impact on the timing properties of short pulse generation circuits and propose a response surface model combined with Latin Hypercube Sampling (LHS) to model the timing jitter.
Journal ArticleDOI
Fast Analysis of Time Interval Error in Current-Mode Drivers
TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.
Journal ArticleDOI
An Efficient Estimation of Power Supply-Induced Jitter by Numerical Method
TL;DR: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach and reports a significant speed-up reported compared with the simulations by a commercial simulator.
Journal ArticleDOI
Predicting Statistical Characteristics of Jitter Due to Simultaneous Switching Noise
TL;DR: Methods using vectorless techniques are presented to predict the mean and standard deviation of the power supply noise on the printed circuit board (PCB), and the mean-to-peak jitter in a driver on the same PCB, sufficient for predicting how a specific logic design might impact jitter and for proposing means to minimize that impact.