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Journal ArticleDOI

Electrical Characteristics of Thermal-SiON-Gated Ge p-MOSFET Formed on Si Substrate

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TLDR
In this paper, the p-MOSFET formed on a thin Ge layer with the thermal SiON as the gate dielectric was electrically characterized, and the desirable passivation of the Ge channel was evidenced by the interface trap density lower than 3.46 times.
Abstract
With a Si substrate, the p-MOSFET formed on a thin Ge layer with the thermal SiON as the gate dielectric was electrically characterized in this letter. The desirable passivation of the Ge channel is evidenced by the interface trap density lower than 3.46 times1011 cm-2middoteV-1. A 1.74 times higher peak hole mobility than that of the Si universal one is obtained by the Ge MOSFET due to the low interface trap density and the good Ge crystallinity. With the source/drain region mainly formed on the Si substrate, the Ge MOSFET also demonstrates the excellent junction leakage. Combining these promising electrical characteristics, the thermal SiON with the device structure holds the potential to be applied to high-performance Ge MOSFETs.

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Citations
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Journal ArticleDOI

Enhanced Hole Mobility and Low $Tinv$ for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

TL;DR: In this article, the authors proposed a pMOSFET device with novel superlattice (SL) SiGe channels to enhance the carrier mobility degraded by ultrathin high-k gate dielectric.
Journal ArticleDOI

Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric

TL;DR: In this article, a thermal SiON film was used as the gate dielectric for metal-oxide-semiconductor (MOS) devices, which achieved an acceptable interface trap density of 7.08x10^1^1cm^-^2eV^-1 close to midgap.
Journal ArticleDOI

Comparison of Ge Surface Passivation Between $ \hbox{SnGeO}_{x}$ Films Formed by Oxidation of Sn/Ge and $ \hbox{SnGe}_{x}/\hbox{Ge}$ Structures

TL;DR: In this paper, X-ray photoelectron spectroscopy was used to investigate the capability of passivation for Ge MOS devices, and it was found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO.
Journal ArticleDOI

Studies on Halo Implants in Controlling Short-Channel Effects of Nanoscale Ge Channel pMOSFETs

TL;DR: In this article, the impact of halo implants on short channel effects of nanoscale Ge channel pMOSFETs in terms of different electrical device parameters such as threshold voltage, subthreshold slope (SS), and drain-induced barrier lowering is reported.
References
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Journal ArticleDOI

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

TL;DR: In this paper, the authors show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions, and that it is possible to both under- and overestimate the interface trap density by more than an order of magnitude.
Journal ArticleDOI

Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric

TL;DR: In this article, the feasibility of integrating a high-permittivity gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates was demonstrated.
Journal ArticleDOI

Electrical characterization of germanium p-channel MOSFETs

TL;DR: In this article, germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer are presented.
Proceedings ArticleDOI

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

TL;DR: In this paper, the authors report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer.
Journal ArticleDOI

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

TL;DR: In this paper, the use of atomic layer deposition (ALD) for high/spl kappa/ gate dielectric formation in Ge MOS devices was presented. But the results were limited to a single-stage MOS device.
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Combining these promising electrical characteristics, the thermal SiON with the device structure holds the potential to be applied to high-performance Ge MOSFETs.