Journal ArticleDOI
Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
TLDR
In this article, a low-temperature process with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (tSi = 30 nm).Abstract:
Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (< 700degC) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (tSi = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 ldr 1015 and 5 ldr 1015 cm-2. Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.read more
Citations
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Journal ArticleDOI
High- $\kappa$ /Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
Marwan H. Khater,Zhen Zhang,Jin Cai,Christian Lavoie,Christopher P. D'Emic,Qingyun Yang,Bin Yang,M. Guillorn,D. Klaus,John A. Ott,Yu Zhu,Ying Zhang,Chang Hwan Choi,Martin M. Frank,Kam-Leung Lee,Vijay Narayanan,Dae-Gyu Park,Q.C. Ouyang,Wilfried Haensch +18 more
TL;DR: In this article, the authors demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal.
Journal ArticleDOI
Interaction of NiSi with dopants for metallic source/drain applications
TL;DR: In this paper, dopant segregation (DS), surface passivation (SP), and alloying have been investigated for reducing the Schottky barrier height (SBH) of NiSi in order to improve the carrier injection into the conduction channel of a field effect transistor.
Journal ArticleDOI
On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain
TL;DR: In this article, the authors focus on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi.
Proceedings ArticleDOI
Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
TL;DR: In this article, an overview of the metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology is provided, which offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from s/D to channel and low temperature processing.
Journal ArticleDOI
Dopant-Segregated Schottky Junction Tuning With Fluorine Pre-Silicidation Ion Implant
Reinaldo A. Vega,Tiehui Liu +1 more
TL;DR: In this article, a fluorine pre-silicidation ion implant (F-PSII) was used to reduce the depth of the doped Si region, which provides a new means for engineering the source/drain extension regions in DSS source-drain MOSFETs.
References
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Journal ArticleDOI
Overview and status of metal S/D Schottky-barrier MOSFET technology
John M. Larson,John P. Snyder +1 more
TL;DR: The metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology as mentioned in this paper offers several benefits that enable scaling to sub-30-nm gate lengths.
Journal ArticleDOI
A spacer patterning technology for nanoscale CMOS
TL;DR: In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.
Journal ArticleDOI
N-type Schottky barrier source/drain MOSFET using ytterbium silicide
Shiyang Zhu,J.D. Chen,Ming-Fu Li,Ming-Fu Li,Sungjoo Lee,Janak Singh,Chunxiang Zhu,Anyan Du,C.H. Tung,Albert Chin,Dim-Lee Kwong +10 more
TL;DR: Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs.
Proceedings ArticleDOI
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
TL;DR: In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.
Journal ArticleDOI
A Comparative Study of Two Different Schemes to Dopant Segregation at NiSi/Si and PtSi/Si Interfaces for Schottky Barrier Height Lowering
TL;DR: In this article, the Schottky barrier height (SBH) of the contact systems of NiSi and PtSi was compared with two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface.
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Overview and status of metal S/D Schottky-barrier MOSFET technology
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