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Proceedings ArticleDOI

Manufacturable 22nm FD-SOI Embedded MRAM Technology for Industrial-grade MCU and IOT Applications

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TLDR
In this paper, a manufacturable 22nm FD-SOI 40Mb embedded MRAM (eMRAM) was demonstrated to achieve product functionality and reliability at package level across industrial-grade operating temperature range (−40 to 125 °C) with ECC-off mode.
Abstract
We demonstrate the manufacturable 22nm FD-SOI 40Mb embedded MRAM (eMRAM), by achieving product functionality and reliability at package level across industrial-grade operating temperature range (−40 to 125 °C) with ECC-off mode. The magnetic tunnel junction stack, integration and etch processes were optimized to achieve superior MTJ performances to meet all product requirements. From package level data, we confirmed the product reliability by passing LTOL, HTOL, 1M endurance cycling and 5x solder reflows tests with failure rate < 1 ppm. In addition, we demonstrate the eMRAM capability to cover stand-by magnetic immunity of ~ 600 Oe at 105 °C for 10 years and active-mode magnetic immunity of ~500 Oe.

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Journal ArticleDOI

Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

TL;DR: In this paper, the authors survey the recent progresses in SRAM and RRAM-based CIM macros that have been demonstrated in silicon and discuss general design challenges of the CIM chips including analog-to-digital conversion bottleneck, variations in analog compute, and device non-idealities.
Journal ArticleDOI

The promise of spintronics for unconventional computing

TL;DR: In this article, the authors discuss how spintronics may aid in the realization of efficient devices, primarily focusing on magnetic tunnel junctions, and provide a perspective on how these devices can impact the development of three unconventional computing paradigms, namely, reservoir computing, probabilistic computing and memcomputing.
Journal ArticleDOI

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

TL;DR: The article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.
Journal ArticleDOI

Scaling magnetic tunnel junction down to single-digit nanometers - Challenges and prospects

TL;DR: The scaling of MTJ technology is reviewed, from in-plane anisotropy MTJs to perpendicular interfacial- or shape-anisotrop MTJs, and challenges and prospects in the future 1X- and X-nm era are discussed.
Journal ArticleDOI

Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM With 10-ns Low Power Write Operation, 10 Years Retention and Endurance > 10¹¹

TL;DR: In this article, a quadruple-interface perpendicular magnetic tunnel junction (MTJ) was fabricated down to 33 nm using physical vapordeposition, reactive ion etching, and damage-control integration process technologies that were developed under a 300mm process.
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