Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation

doi:10.1109/SISPAD.2018.8551641

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Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation

Proceedings Article•DOI•

Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation

Juan Pablo Duarte¹, Yen-Kai Lin¹, Yu-Hung Liao¹, Angada B. Sachid¹, Ming-Yen Kao¹, Harshit Agarwal¹, Pragya Kushwaha¹, Korok Chatterjee¹, Daewoong Kwon¹, Huan-Lin Chang¹, Sayeef Salahuddin¹, Chenming Hu¹ - Show less +8 more•Institutions (1)

University of California, Berkeley¹

28 Nov 2018-pp 123-128

TL;DR: In this article, a complete simulation framework for Negative Capacitance FinFETs including numerical simulation, compact model, and circuit evaluation is presented, where the influence of short-channel effects in Ferroelectric voltage amplification is incorporated.

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Abstract: A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.

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Journal Article•DOI•

Spacer Engineering in Negative Capacitance FinFETs

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Yen-Kai Lin¹, Harshit Agarwal¹, Ming-Yen Kao¹, Jiuren Zhou¹, Yu-Hung Liao¹, Avirup Dasgupta¹, Pragya Kushwaha¹, Sayeef Salahuddin¹, Chenming Hu¹ - Show less +5 more•Institutions (1)

University of California, Berkeley¹

15 Apr 2019-IEEE Electron Device Letters

TL;DR: In this article, the spacer design of the negative-capacitance FinFET (NC-FinFET) was investigated by using Sentaurus technology computer-aided design (TCAD).

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Abstract: The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance.

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35 citations

Cites background from "Negative-Capacitance FinFETs: Numer..."

...However, with the concern of capacitance matching in NC-FinFET [25],...
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Journal Article•DOI•

Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

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Yen-Kai Lin¹, Harshit Agarwal¹, Pragya Kushwaha¹, Ming-Yen Kao¹, Yu-Hung Liao¹, Korok Chatterjee¹, Sayeef Salahuddin¹, Chenming Hu¹ - Show less +4 more•Institutions (1)

University of California, Berkeley¹

05 Mar 2019-IEEE Transactions on Electron Devices

TL;DR: In this paper, the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node was investigated.

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Abstract: We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.

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32 citations

Cites background from "Negative-Capacitance FinFETs: Numer..."

...[20] recently reported that the fringing fields impact the subthreshold characteristics of NCFETs, the detailed analysis of the FE properties across the channel and its impact on the ON current remain absent....
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Journal Article•DOI•

Recent Advances in Negative Capacitance FinFETs for Low-Power Applications: A Review

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Vibhuti Chauhan¹, Dip Prakash Samajdar¹•Institutions (1)

Indian Institutes of Information Technology¹

08 Jul 2021-IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control

TL;DR: In this article, the negative capacitance fin field effect transistors (NC-FinFETs) came up as the next-generation platform to withstand the aggressive scaling of transistors.

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Abstract: In the contemporary era of Internet-of-Things (IoT), there is an extensive search for competent devices which can operate at ultralow voltage supply. Due to the restriction of power dissipation, a reduced sub-threshold swing-based device appears to be the perfect solution for efficient computation. To counteract this issue, negative capacitance fin field-effect transistors (NC-FinFETs) came up as the next-generation platform to withstand the aggressive scaling of transistors. The ease of fabrication, process-integration, higher current driving capability, and ability to tailor the short-channel effects (SCEs) are some of the potential advantages offered by NC-FinFETs that attracted the attention of researchers worldwide. The following review emphasizes how this new state-of-art technology supports the persistence of Moore’s law and addresses the ultimate limitation of Boltzmann tyranny by offering a sub-threshold slope (SS) below 60 mV/decade. The article primarily focuses on two parts: 1) the theoretical background of negative capacitance (NC) effect and FinFET devices and 2) the recent progress done in the field of NC-FinFETs. It also highlights the crucial areas that need to be upgraded, to mitigate the challenges faced by this technology and the future prospects of such devices.

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20 citations

Journal Article•DOI•

Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

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Yu-Hung Liao¹, Daewoong Kwon¹, Yen-Kai Lin¹, Ava J. Tan¹, Chenming Hu¹, Sayeef Salahuddin¹ - Show less +2 more•Institutions (1)

University of California, Berkeley¹

12 Sep 2019-IEEE Electron Device Letters

TL;DR: The negative capacitance field effect transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOS FET theory.

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Abstract: The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit.

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18 citations

Cites background from "Negative-Capacitance FinFETs: Numer..."

...The increase of ferroelectric polarization due to the inner fringing field [11], [12] contributes to the Lg-dependent potential amplification effect, which translates to gate stack capacitance improvement in short-channel NCFETs....
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Journal Article•DOI•

Sustained Benefits of NCFETs Under Extreme Scaling to the End of the IRDS

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Thomas Cam¹, Ji Kai Wang¹, Michael Wong¹, Kyle Holland², Prasad S. Gudem³, Diego Kienle⁴, Mani Vaidyanathan¹ - Show less +3 more•Institutions (4)

University of Alberta¹, Qualcomm², University of California, San Diego³, University of Bayreuth⁴

29 Jul 2020-IEEE Transactions on Electron Devices

TL;DR: In this article, the authors use full quantum-transport simulations by coupling the Landau-Khalatnikov (LK) and Poisson equations self-consistently with the nonequilibrium Green's function (NEGF) formalism, and calibrated to experimental results, to investigate extremely scaled negative-capacitance, field effect transistors (NCFETs) having dimensions toward the end of the international roadmap for devices and systems (IRDS), that is, to sub-10-nm gate lengths, where channel transport can be expected to be governed by

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Abstract: We use full quantum-transport simulations by coupling the Landau–Khalatnikov (LK) and Poisson equations self-consistently with the nonequilibrium Green’s function (NEGF) formalism, and calibrated to experimental results, to investigate extremely scaled negative-capacitance, field-effect transistors (NCFETs) having dimensions toward the end of the international roadmap for devices and systems (IRDS), that is, to sub-10-nm gate lengths, where channel transport can be expected to be governed by quantum-mechanical effects. We identify how the ferroelectric affects both thermionic emission and quantum-mechanical tunneling of electrons, both of which are relevant transport mechanisms for these ultrascaled devices. Our detailed results show that while NCFETs are not immune to the increase in the tunneling as they undergo extreme channel-length scaling, the metal–ferroelectric–insulator–semiconductor (MFIS) structure will continue to offer benefits to a subthreshold slope, ON- and OFF-currents, drain-induced barrier lowering, and output conductance until the end of the roadmap. These improvements allow MFIS NCFETs of any given node to achieve similar performance to nonferroelectric devices of the immediately preceding (higher-dimension) node. The fundamental reason for the improvements is identified to be the presence of voltage amplification at the top of the barrier (TOB) and suppression of TOB movement with drain voltage.

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8 citations

Cites background from "Negative-Capacitance FinFETs: Numer..."

...Finally, although there is an improvement in DIBL and go in the MFIS NCFETs, they are not negative, an outcome of a relatively small k in (1), and consistent with the results of Lin et al. [14]....
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...In [12] and [13], NCFET performance from extremely long to modern channel lengths (1000–16 nm) was examined using a drift–diffusion formulation, while Lin et al. [14] and Liao et al. [15] identified fringing fields in an MFIS structure as a key feature of NCFET performance as the channel length scales down from 80 to 16 nm. Electrostatic integrity of MFIS NCFETs has been demonstrated using different permittivity spacers to improve both drain-induced barrier lowering (DIBL) and SS for gate lengths down to 16 nm [16]....
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...Capacitance matching for MFIS NCFETs has also been optimized to improve performance, including the investigation of the maximum electric field required to keep the ferroelectric in the negative capacitance region [17] and the achievement of matching by using a nonuniform thickness in the ferroelectric layer [18] or two ferroelectric oxides [19], all of which have 0018-9383 © 2020 IEEE....
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...Other work on MFIS NCFETs [20]–[24] has shown that the MFIS structure provides benefits to short-channel effects, as measured in this article by DIBL and output conductance go, and an improvement to both SS and ION/IOFF, over a baseline device having no ferroelectric....
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...Short-channel MFIS NCFETs have previously been studied using a variety of techniques [11]–[29]....
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References

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Journal Article•DOI•

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

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Sayeef Salahuddin¹, Supriyo Datta¹•Institutions (1)

Purdue University¹

01 Feb 2008-Nano Letters

TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.

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Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

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1,722 citations

"Negative-Capacitance FinFETs: Numer..." refers background in this paper

...11 shows a comparison of the voltages at the first node of the RO under study utilizing base-line ULP 14nm FinFETs versus NC-FinFETs....
[...]
...As gate length is reduced, NC-FinFETs provide substantial improvements to baseline FinFETs, making them perfect candidates for extremely scaled technologies (Fig....
[...]
...The presented compact model has been implemented in commercial circuit simulators, where 14nm ULP FinFETs [6] are used as baseline technology for the energy evaluation of a ring-oscillator (RO) circuit using NC-FinFETs (Fig....
[...]
...Negative capacitance FinFETs (NC-FinFETs) [1] (Fig....
[...]
...The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology [2] has led to the first demonstrations of FE based NC-FinFETs [3]....
[...]

Journal Article•DOI•

Ferroelectricity in Simple Binary ZrO2 and HfO2

[...]

Johannes Müller, T. S. Böscke¹, Uwe Schröder¹, Stefan Mueller, D. Bräuhaus², Ulrich Böttger², Lothar Frey³, Thomas Mikolajick - Show less +4 more•Institutions (3)

Qimonda¹, RWTH Aachen University², Fraunhofer Society³

23 Jul 2012-Nano Letters

TL;DR: A structural investigation revealed the orthorhombic phase to be of space group Pbc2(1), whose noncentrosymmetric nature is deemed responsible for the spontaneous polarization in this novel, nanoscale ferroelectrics.

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Abstract: The transition metal oxides ZrO2 and HfO2 as well as their solid solution are widely researched and, like most binary oxides, are expected to exhibit centrosymmetric crystal structure and therewith linear dielectric characteristics. For this reason, those oxides, even though successfully introduced into microelectronics, were never considered to be more than simple dielectrics possessing limited functionality. Here we report the discovery of a field-driven ferroelectric phase transition in pure, sub 10 nm ZrO2 thin films and a composition- and temperature-dependent transition to a stable ferroelectric phase in the HfO2–ZrO2 mixed oxide. These unusual findings are attributed to a size-driven tetragonal to orthorhombic phase transition that in thin films, similar to the anticipated tetragonal to monoclinic transition, is lowered to room temperature. A structural investigation revealed the orthorhombic phase to be of space group Pbc21, whose noncentrosymmetric nature is deemed responsible for the spontaneous...

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1,161 citations

"Negative-Capacitance FinFETs: Numer..." refers background in this paper

...ventional CMOS fabrication technology [2] has led to the first demonstrations of FE based NC-FinFETs [3]....
[...]

Proceedings Article•DOI•

14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications

[...]

Zoran Krivokapic¹, Uzma Rana¹, Rohit Galatage¹, Ali Razavieh¹, Ahmedullah Aziz¹, Jinping Liu¹, Jiajun Shi¹, H. J. Kim¹, Ryan Sporer¹, Claudy Serrao¹, A. Busquet¹, P. Polakowski, Johannes Müller, Walter Kleemeier¹, Jacob Ajey Poovannummoottil¹, D. Brown¹, Andreas Knorr¹, Rick Carter¹, Srinivasa Banna¹ - Show less +15 more•Institutions (1)

GlobalFoundries¹

01 Dec 2017

TL;DR: In this paper, Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification.

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Abstract: Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and I dsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.

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179 citations

"Negative-Capacitance FinFETs: Numer..." refers background in this paper

...11 shows a comparison of the voltages at the first node of the RO under study utilizing base-line ULP 14nm FinFETs versus NC-FinFETs....
[...]
...As gate length is reduced, NC-FinFETs provide substantial improvements to baseline FinFETs, making them perfect candidates for extremely scaled technologies (Fig....
[...]
...The presented compact model has been implemented in commercial circuit simulators, where 14nm ULP FinFETs [6] are used as baseline technology for the energy evaluation of a ring-oscillator (RO) circuit using NC-FinFETs (Fig....
[...]
...ventional CMOS fabrication technology [2] has led to the first demonstrations of FE based NC-FinFETs [3]....
[...]
...The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology [2] has led to the first demonstrations of FE based NC-FinFETs [3]....
[...]

Proceedings Article•DOI•

Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

[...]

Juan P. Duarte¹, Sourabh Khandelwal¹, Asif Islam Khan¹, Angada B. Sachid¹, Yen-Kai Lin¹, Huan-Lin Chang¹, Sayeef Salahuddin¹, Chenming Hu¹ - Show less +4 more•Institutions (1)

University of California, Berkeley¹

01 Dec 2016

TL;DR: In this article, the authors propose a lumped and distributed charge model for negative capacitance FinFETs, where the ferroelectric layer will impact the local channel charge and this distributed effect has important implications on device characteristics.

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Abstract: This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.

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75 citations

"Negative-Capacitance FinFETs: Numer..." refers background or methods in this paper

...1), the distributed charge model should be used [4], where at each point in the channel the FE layer will impact the local channel charge (Fig....
[...]
...The charge obtained is used in the Drain-Current model which is computed using Gauss-Quadrature integration [4]....
[...]
...The distributed compact model [4] utilizing the Unified Compact Model [5] and Landau FE model calculates the charge along the gate length direction....
[...]

Proceedings Article•DOI•

A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products

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C.-H. Jan¹, F. Al-Amoody¹, Chang Hsu-Yu¹, Tsung-Yuan Chang¹, Y.-W. Chen¹, N. L. Dias¹, Hafez Walid M¹, D. Ingerly¹, M. Jang¹, Eric Karl¹, S. K.-Y. Shi¹, K. Komeyli¹, H. Kilambi¹, A. Kumar¹, K. Byon¹, Chen-Guan Lee¹, J. Lee¹, T. Leo¹, Pei-Chi Liu¹, Nidhi Nidhi¹, Olac-Vaw Roman W¹, C. Petersburg¹, K. Phoa¹, Chetan Prasad¹, C. Quincy¹, Ramaswamy Rahul¹, T. Rana¹, L. Rockford¹, Anand Subramaniam¹, Curtis Tsai¹, P. Vandervoorn¹, L. Yang¹, A. Zainuddin¹, P. Bai¹ - Show less +30 more•Institutions (1)

Intel¹

17 Jun 2015

TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.

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Abstract: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

...read moreread less

71 citations

"Negative-Capacitance FinFETs: Numer..." refers methods in this paper

...simulators, where 14nm ULP FinFETs [6] are used as base-...
[...]
...Drain current versus VGS for nmos and pmos base-line 14nm ULP FinFET [6], and NC-FinFETs with parasitic capacitance....
[...]
...The presented compact model has been implemented in commercial circuit simulators, where 14nm ULP FinFETs [6] are used as baseline technology for the energy evaluation of a ring-oscillator (RO) circuit using NC-FinFETs (Fig....
[...]