NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Dissertation
Fast CMOS buffering with post-change logic
TL;DR: Post-Charge Logic, a recently developed dynamic circuit form is adapted to the buffering of static signals, showing how the noise vulnerabilities which normally afflict the underlying PCL circuit elements used in this new static buffering scheme can be controlled.
Journal ArticleDOI
Design and Analysis of Digital Ratioed Compressors for Inner Product Processing
TL;DR: The theoretical analysis and Verilog simulation both indicate that one of the compressor building blocks presented here might offer a sub-optimal solution for the basic building blocks used in digital hardware realization of the inner product computation.
Dissertation
Bounding of switching activity in logic circuits
Eduard Cerny,Jindrich Zejda +1 more
TL;DR: The thesis presents algorithms, implementation, and results of a new method based on constraint resolution for finding an upper bound on switching activity in the combinational part of a synchronous sequential circuit and shows that each heuristic is more suitable for a different type of circuit.
Book ChapterDOI
Novel Two-Bit Magnitude Comparators for IOT Applications
TL;DR: In this article , the authors proposed three magnitude comparators that operate on a minimal amount of power and energy, and compared them with the existing two-bit comparators in terms of power losses, latency, transistor count and power delay product.
References
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Journal ArticleDOI
High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Journal ArticleDOI
Clocked CMOS calculator circuitry
Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
TL;DR: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail.
Journal ArticleDOI
High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.