NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
More filters
Journal ArticleDOI
CMOS Shift Register Circuits for Radiation-Tolerant VLSI's
TL;DR: In this article, a radiation-tolerant VLSI circuits investigation has been carried out using CMOS/SOS shift registers, and the performance degradation is discussed, based on MOS FET parameter shifts due to radiation effects, utilizing?-ray irradiation and SPICE simulation.
Proceedings ArticleDOI
A pipelined 32b microprocessor with 13Kb of cache memory
TL;DR: In this paper, a reduced instruction set (RISC) computer with 172k transistors in 1.5μm technology is described. The chip contains caches for prefetch buffer, decoded instructions and stack.
Proceedings ArticleDOI
Fast and scalable priority encoding using static CMOS
TL;DR: The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation and increases with the number of priority encoder bits.
Patent
CMOS skewed static logic and method of synthesis
Chulwoo Kim,Sung-Mo Kang +1 more
TL;DR: In this paper, a new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit, where the output transistors are configured to receive a first input signal to precharge an output of the skewed static gate prior to the skewed gate receiving a second input signal.
Journal ArticleDOI
Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system
R. Jain,Francky Catthoor,J. Vanhoof,B. De Loore,G. Goossens,N.F. Goncalvez,Luc Claesen,J. Van Ginderdeuren,Joos Vandewalle,H. De Man +9 more
TL;DR: The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented and it is shown that by combining both synthesis as well as optimization aids at each design level, it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput and moderate power consumption.
References
More filters
Journal ArticleDOI
High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Journal ArticleDOI
Clocked CMOS calculator circuitry
Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
TL;DR: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail.
Journal ArticleDOI
High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.