NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Journal ArticleDOI
Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels
W.A.M. Van Noije,G.J. Declerck +1 more
TL;DR: A description of a novel CMOS gate array architecture for LSI/VLSI complexity based on the `gate isolation' technique for logic implementation, in addition to the programmability of the amount of routing channels, which uses double-level metal with the first contact level programmable for the circuit customization.
Journal ArticleDOI
Skewed CMOS: noise-tolerant high-performance low-power static circuit family
TL;DR: A noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic, designed using skewed logic circuits and fabricated through MOSIS, which has better scalability and better noise margins than Domino logic.
Journal ArticleDOI
Wave-domino logic: theory and applications
Wei-Han Lien,Wayne Burleson +1 more
TL;DR: In this paper, a wave-domino multiplier, sum of product trees, and parity checker are implemented in a CMOS domino circuit with a clock period smaller than the latency of the combinational block.
Journal ArticleDOI
Latched domino CMOS logic
TL;DR: A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented, which can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area.
Proceedings ArticleDOI
Dynamic logic synthesis
Gin Yee,Carl Sechen +1 more
TL;DR: A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs and its characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits.
References
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Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
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High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.