NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Book ChapterDOI
Towards a framework for dealing with system timing in Very High Level Silicon Compilers
TL;DR: A framework for dealing with system timing issues in the context of very high level silicon compilers intended to aid in mapping abstract behavioral specifications into VLSI circuits is discussed.
Journal ArticleDOI
CMOS on-chip clock for digital signal processors
TL;DR: An on-chip clock for frequencies up to 190 MHz is presented, which can be used for application specific digital signal processors which are clocked faster than the off-chip system clock.
Proceedings ArticleDOI
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic
TL;DR: Experimental results showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power delay by 20-37%.
Journal ArticleDOI
A stuck fault model for dynamic CMOS combinational circuits
TL;DR: In this paper, the authors used the logic transistor function (LTF) to model the static CMOS combinational circuits at the transistor and logic level, and used the LTF to generate fault-free and faulty LTFs for different implementations of the dynamic CMOS circuit.
Proceedings ArticleDOI
New CMOS differential logic circuits for true-single-phase pipelined systems
Hong-Yi Huang,Chung-Yu Wu +1 more
TL;DR: A set of new CMOS differential logic circuits are proposed for the true-single-phase clocking scheme in the pipelined systems and can be applied to high-packing-density and high-speed CMOS pipelining systems.
References
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Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
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