NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Testing of zipper CMOS logic circuits
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TL;DR: Zipper CMOS is a dynamic CMOS circuit technique which also provides protection against instability and charge-sharing problems; this is achieved by using a special driver circuit and enjoys a huge testability advantage over static CMOS circuits.
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Efficient verification of VLSI circuits based on syntax and denotational semantics
TL;DR: Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
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Dissertation
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline
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References
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High-speed compact circuits with CMOS
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Journal ArticleDOI
Clocked CMOS calculator circuitry
Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
TL;DR: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail.
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High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.