NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Proceedings ArticleDOI
Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs
TL;DR: Two fast half-swing CMOS circuits for NOR-NOR PLA implementation are presented to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced.
Journal Article
High Performance Logic Style with Constant Delay characteristics and Self-Reset Circuitry
TL;DR: The concept of Constant Delay Logic is extended to SR Latch and 8-bit Comparator and it is found that in 32nm technology CD Logic delay is less by 96% and 68% in comparison with Static and Dynamic logics respectively.
Proceedings ArticleDOI
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism
Ching-Hwa Cheng,Jiun-In Guo +1 more
TL;DR: The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology.
Arbitrary Circuits Using Modified Constant Delay Technique
TL;DR: This paper perceives Pre evaluation of output before the arrival of inputs from the preceding stages is ready becomes an added advantage of MCD logic style and achieves meliorate performance and is more energy efficient than the other logic styles for the implementation on arbitrary circuits.
Book ChapterDOI
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
TL;DR: In this comunication, a new technique to generate flip-flops based on differential structures based on the modification of size in transistors of existing differential latches is presented, and the behavior is similar in both the proposed flip- Flop and the original structure, and better than existing flip- flops.
References
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Journal ArticleDOI
High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Journal ArticleDOI
Clocked CMOS calculator circuitry
Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
TL;DR: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail.
Journal ArticleDOI
High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.