NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TLDR
A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.Abstract:
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.read more
Citations
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Journal ArticleDOI
Three alternative architectures of digital ratioed compressor design with application to inner-product processing
TL;DR: Three alternative architecture for arranging digital ratioed compressors are presented, to reduce the carry propagation delay in the critical path wherein an improved design of a 3-2 compressor is used to serve as the basic building element.
Book ChapterDOI
MOS Digital Integrated Circuits
TL;DR: Circuit techniques as well as circuit structures are presented including CMOS transmission gate logic, dynamic CMOS, domino logic, NORA and Zipper circuit structures, CMOS nonthreshold logic and cascade voltage switch logic.
Testing of Multiple- Output Domino Logic
TL;DR: It is shown that due to the greater observability of MODL circuits, their test sets can be considerably smaller than those derived for the conventional domino CMOS circuits, which should turn out to be an attractive CMOS logic technology.
Proceedings ArticleDOI
A 1.5 V CMOS high-speed 16-bit/spl divide/8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
C.-C. Yeh,J.H. Lou,James B. Kuo +2 more
TL;DR: Based on a 0.8 /spl mu/m CMOS technology, the speed performance of this 16-bit/spl divide/8-bit divider circuit is improved by 45% as compared to the divider using the non-restoring iterative architecture and the domino dynamic logic circuits without the bootstrapped technique.
Proceedings ArticleDOI
Two phase nonoverlapping clocked All-N-Logic in subthreshold region with 49fJ power delay product
TL;DR: This paper represents a new structure of ANL logic, named TPSANL to achieve ultra low power with no glitches in the subthreshold region by using two phase nonoverlapping clocks to eliminate output glitches and reduces the glitch power.
References
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Journal ArticleDOI
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Y. Suzuki,M. Hirasawa,K. Odagawa +2 more
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High-density CMOS ROM arrays
TL;DR: The CMOSROMs produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl Deg/C temperature range.
Proceedings Article
NP-CMOS: A Racefree - Dynamic CMOS Technique for Pipelined Logic Structures
N.F. Gqncalves,H. De Man +1 more
TL;DR: In this paper, a new dynamic CMOS circuit technique using n and p logic trees is presented, which operates race-free from two clocks O and O regardless of their overlap time.
Journal ArticleDOI
High-speed programmable logic arrays in ESFI SOS technology
E. Hebenstreit,K. Horninger +1 more
TL;DR: Exploratory MOS programmable logic arrays (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated as discussed by the authors, and the problems arising with the use of these dynamic logic gates are discussed and different circuits are presented.