Showing papers on "Bipolar junction transistor published in 1990"

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

Abstract: The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps. >

Impact ionization in silicon: A review and update

Abstract: After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

MOS device for long-term learning

Abstract: A semiconductor structure for long-term learning includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region. A polysilicon floating gate is separated from the surface of the silicon substrate by a gate oxide and is positioned above the well region. One edge of the polysilicon floating gate is aligned with the edge of the n-type region within the well region such that the polysilicon floating gate does not appreciably overly the n-type region. The substrate, the well, and the n-type region, respectively, form the emitter, base, and collector of a bipolar transistor.

Smart temperature sensor in CMOS technology

Abstract: A CMOS monolithic temperature sensor is described, based on compatible lateral bipolar transistors for the sensor part and the reference, and on CMOS circuits for A/D conversion, control and calibration. The accuracy of the analog part is close to the performances obtained in bipolar technology, for example ± 0. 1 °C in a 60 °C temperature range, and it is maintained on conversion. CMOS flexibility allows adaption of the digital output signal to any temperature scale and storage of the calibration bits in an EEPROM on the chip. The circuit works in a 2.5 to 5 V range and draws 50 μA current. A 1.5 V version with reduced accuracy is also feasible.

The DC characteristics of GaAs/AlGaAs heterojunction bipolar transistors with application to device modeling

Abstract: A complete DC model for the heterojunction bipolar transistor (HBT) is presented. The DC characteristics of the HBT are compared with the Ebers-Moll (EM) model used by conventional bipolar junction transistors (BJTs) and implemented in simulation and modeling programs. It is shown that although the details of HBT operation can differ markedly from those of a BJT, a model and a parameter extraction technique can be developed which have physical meaning and are exactly compatible with the EM models widely used for BJTs. Device I-V measurements at 77 and 300 K are used to analyze the HBT physical device performance in the context of an EM model. A technique is developed to extract the device base, emitter, and collector series resistances directly from the measured I-V data without requiring an ideal exp(qV/sub be//kT) base current as reference. Accuracies of the extracted series resistances are assessed. AC parameters of HBT are calculated numerically from the physical device structure. For modeling purposes, these parameters are shown to be comparable with those of conventional BJTs. >

Emitter size effect on current gain in fully self-aligned AlGaAs/GaAs HBT's with AlGaAs surface passivation layer

Abstract: The emitter size effect for fully self-aligned AlGaAs-GaAs heterojunction bipolar transistors (HBTs) with depleted AlGaAs passivation layers, in which the partially thinned AlGaAs emitter is self-aligned by using the dual sidewall process, is investigated. It is demonstrated that drastic improvement in the emitter size effect can be achieved with an AlGaAs passivation layer as small as 0.2 mu m in width, due to the surface recombination current reduction by a factor of 1/40 in the extrinsic base region. It has also been found that the base current is dominated by excess leakage current in the proton-implanted isolation region. >

Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits

Abstract: A linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed. It is found that the behavior of the propagation delay is quite linear, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of the expressions is checked by SPICE simulations and comparison to experimental data published in the literature, and agreement is within 5%. The expressions indicate that there is an optimum value of load resistance for logic circuits in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density corresponding to maximum f/sub T/, and logic circuits for AlGaAs-GaAs heterojunction bipolar transistors (HBTs) should operate at a current density lower than that of maximum f/sub T/. Therefore, it is important to increase the collector current density of maximum f/sub T/ for silicon bipolar circuits, or to decrease the base resistance R/sub B/ and the forward transit time tau /sub F/ for HBT circuits, in order to increase the circuit speed. >

Characterization of GaAs/Ga1−xAlxAs heterojunction bipolar transistor structures using photoreflectance

Abstract: We have studied the photoreflectance spectra at 300 K from a number of GaAs/Ga1−x AlxAs heterojunction bipolar transistor (HBT) structures grown by molecular beam epitaxy and metalorganic chemical vapor deposition. From the observed Franz–Keldysh oscillations we have been able to evaluate the built‐in dc electric fields Fdc in the Ga1−x Alx As emitter as well as the n−‐GaAs collector region. In addition, the Ga1−x Alx As band gap (and hence Al composition) has been determined. The obtained values of Fdc are in good agreement with numerically computed values for the analyzed HBT structures, thus making it possible to deduce doping levels in these sections.

Integrated circuit composed of group III-V compound field effect and bipolar semiconductors

Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.

Complementary bipolar transistor structure and method for manufacture

Abstract: A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etchig a shallow trench in the first layer and depositing semiconductor material of a second conductivity tyep by LTE and planarizing. The intrinsic regions for both of the transistors are formed by depositing a second layer of semiconductor material of the second conductivity type on the surface of the first layer and a third layer of semiconductor material of the first conductivity type on the surface of the second layer by either LTE or MBE. In one embodiment, the second and third layers are provided with a uniform vertical doping profile for one thickness of the layer and a graded doping profile for the remaining thickness in which the minimum doping level for both graded portions is at the junction between the second and third layers. The second layers forms the base and the third layer forms the collector for one transistor while at the same time the second layer forms a collector and the third layer forms the base for the other transistor. The performance of the intrinsic base and collector regions can be further improved by forming the second and third layers with a compound semiconductor material, such as, the compound of Si-Ge to create a heterojunction transistor. Device and intrinsic region isolation is effected by a combination of deep trench and shallow trench processes and reach-through regions for the sub-emitter and sub-collector are formed. A layer of polysilicon is deposited and selectively etched to form an extrinsic collector region for one transistor and extrinsic base regions for the other transistor. A further loayer of single crystal silicon is deposited to form the extrinsic base region for one transistor and the emitter for the other transistor.

Non-equilibrium modes of operation of narrow-gap semiconductor devices

Abstract: Research work is reviewed which uses the phenomena of minority carrier extraction and minority carrier exclusion to reduce the carrier densities in narrow-gap Hg1-xCdxTe alloys to near-extrinsic values at temperatures where the materials are normally intrinsic. This is of particular interest for the suppression of Auger noise which otherwise severely limits the performance achievable from infrared detectors at near-ambient operating temperatures. Improved performance has been obtained from excluding photoconductive detectors at modulation frequencies above 10 kHz. Theoretical work predicts improved performance from heterojunction extracting diodes. Early experiments on 'proximity-extracting' diode structures show large reductions in leakage current at intermediate and ambient temperatures compared to non-extracted diodes, but the residual current is higher than that predicted from Shockley-Read generation. Bipolar transistor action is observed at temperatures where the material is near-intrinsic in equilibrium. The transistor characteristics are strongly influenced by electron impact ionisation.

The impact of non-equilibrium transport on breakdown and transit time in bipolar transistors

Abstract: Impact ionization and velocity overshoot in the base-collector junction of bipolar transistors are studied using Monte Carlo simulation and the hydrodynamic energy-balance equation. For advanced bipolar transistors, the carrier energy lags the electric field; therefore, the maximum impact ionization rate occurs deep into the junction. A simplified solution of the energy-balance equation can accurately model this nonlocal behavior. Excellent agreement with measurements of the multiplication factor for a variety of base-collector profiles is obtained. As a consequence of this nonequilibrium effect, velocity overshoot is expected and its trade-off with breakdown is analyzed in detail. >

Carbon-doped base GaAs/AlGaAs heterojunction bipolar transistor grown by metalorganic chemical vapor deposition using carbon tetrachloride as a dopant source

Abstract: Carbon tetrachloride (CCl4) has been used as a carbon doping source for the base region of a GaAs/AlGaAs Npn heterojunction bipolar transistor (HBT) grown by low‐pressure metalorganic chemical vapor deposition (MOCVD). Transistors were fabricated and characterized for dc current gain, emitter‐base junction ideality factor, base contact resistance, and external base resistance. Microwave characterization by S‐parameter measurement was performed to determine the common emitter current gain and maximum available gain as a function of frequency. Transistors with the base contact area self‐aligned to a 3×10 μm emitter finger had a dc current gain as high as 50, an emitter‐base junction ideality factor of n=1.2, and a current gain cutoff frequency of ft=26 GHz. Transistors of equal emitter area without self‐alignment exhibited dc current gain as high as 86, n=1.2, and ft=20 GHz. A base contact resistance of Rc=2.85×10−6 Ω cm2 and an external base sheet resistance of Rs=533.4 Ω/⧠ were measured. These preliminary...

Latchup in CMOS from single particles

Abstract: Single-particle latchup in bulk CMOS was examined using heavy ions, a californium fission source, and a pulsed laser. Experiments with the laser demonstrated that latchup triggering was caused by secondary photocurrent in either the vertical or lateral parasitic transistor. Charge diffusion is shown to be important for bipolar transistor responses in latchup, which in turn makes it important to have uniform charge deposition for depths of 10 mu m or more. Californium sources have insufficient range, which causes cross sections measured with californium to be much lower than cross sections from heavy ion experiments. >

Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip

Abstract: A process is used to form in a common substrate (12) a PMOS transistor (200) of the lightly-doped drain (LDD) type, an NMOS transistor (100) of the LDD type and a vertical n-p-n bipolar transistor (300). In particular: the steps used to form an n-type well (214) for the PMOS transistor (200), and an n-type drain extension well (114) for the NMOS transistor (100), are also used to form the n-type collector (314) of the bipolar transistor (300); the steps used to form the p-type extension well (208) for the PMOS transistor (200) are also used to form the p-type base (308) of the bipolar transistor (300), the source/drain implantation step for the NMOS transistor (100) is also used to form the emitter (310) and a contact region (312) for the collector of the bipolar transistor (300); and the source/drain implantation step for the PMOS transistor (200) is used to form a contact region (311) for the base of the bipolar transistor (300).

A Gummel-Poon model for abrupt and graded heterojunction bipolar transistors (HBTs)

Abstract: A Gummel-Poon model for abrupt and graded GaAlAs/GaAs/GaAs heterojunction bipolar transistors (HBTs) is developed. The effect of carrier recombination at the emitter-base heterojunction, space charge region (SCR) width modulation effect, and base-widening effect at large collector currents have been considered. Results from this model are compared with numerical results, experimental results, and results from the most recent analytical models. The results show that the common-emitter current gain behavior in the low collector current region can be predicted more accurately by this model, and that interface and surface recombination affect the current gain more dominantly than the other recombination processes. Dependence of cutoff frequency on collector current obtained from the present model agrees well with the experimental results. This model can also predict both current gain and cutoff frequency falloffs at large collector current. This model can be easily implemented in the SPICE program.

Picosecond noninvasive optical detection of internal electrical signals in flip-chip-mounted silicon integrated circuits

Abstract: This paper reviews the charge-sensing optical probing system, and shows how it may be used to detect internal current and voltage signals in flip-chip-mounted silicon integrated circuits. Previously, researchers have used this concept to detect both single-shot 200-MHz-bandwidth signals, without averaging, and 8-GHz-bandwidth stroboscopic signals. This system has a high sensitivity: 145nA/√Hz current sensitivity in typical bipolar transistors, and 1.35mV/√Hz voltage sensitivity in typical CMOS circuits (using a semiconductor laser probe). It is noninvasive, has a potential submicron spatial resolution, and should be capable of providing linear and calibrated measurements. Therefore, this probing approach should be a powerful tool for future circuit analysis and testing.

Extraction of the parameters of equivalent circuits of microwave transistors using tree annealing

Abstract: The problem of extracting a physically based equivalent circuit model for a heterostructure bipolar transistor (HBT) from S-parameter measurements is solved with a new formulation of simulated annealing. The physical model necessary for an accurate representation of the HBT leads to an extraction problem with many local minima. A satisfactory minimum can be found by conventional gradient-based techniques only with considerable expert guidance. The proposed algorithm finds equivalent circuits as good as those from conventional techniques but without human intervention. It is more efficient than conventional stochastic simulated annealing because it accumulates a probability density of good equivalent circuits which it subsequently uses to refine its statistical search for the best equivalent circuit. >

Implant isolation of GaAs‐AlGaAs heterojunction bipolar transistor structures

Abstract: The formation of high‐resistivity (>107Ω/⧠) regions in GaAs‐AlGaAs heterojunction bipolar transistor (HBT) structures by oxygen and hydrogen ion implantation has been investigated as a function of ion dose and subsequent annealing temperature (400–700 °C). Isolation leakage currents as low as 8 μA mm−1 at 6 V can be achieved between 100‐μm‐wide ohmic contacts separated by a 16 μm spacing. The isolation of these 1.8‐μm‐thick heterojunctions requires up to six different energy oxygen implants (40–400 keV) and three different energy proton implants (100–200 keV) with doses in the mid 1012 cm−2 range for O+ and 5×1014 cm−2 for H+ ions. Similar results can be achieved by substituting a MeV energy oxygen implant for the proton implants. The optimum post‐implant annealing temperature depends on the ion dose but is in the range 500–600 °C. The evolution of the sheet resistance of the implanted GaAs‐AlGaAs material with annealing is consistent with a reduction in tunneling probabilities of trapped carriers between deep level states for temperatures up to ∼600 °C, followed by significant annealing of these deep levels. Small geometry (2×9 μm2) HBTs exhibiting current gain of 44 and cutoff frequency fT as high as 45 GHz are demonstrated using implant isolation.

4 Gbit/s pin/HBT monolithic photoreceiver

Abstract: Heterojunction bipolar transistors have been monolithically integrated with a pin photodetector to realise a high speed transimpedance photoreceiver. The OEIC, made from MOVPE-growth InP/InGaAs heterostructures, had a bandwidth of 2.8 GHz with a transimpedance of 750 Ω. It was successfully operated at 4 Gbit/s with a sensitivity of −21 dBm at a wavelength of 1.5 μm.

Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology

Abstract: The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement. >

Reliability analysis of GaAs/AlGaAs HBTs under forward current/temperature stress

Abstract: The reliability of GaAs/AlGaAs heterojunction bipolar transistors is investigated by accelerated life-testing of discrete devices under forward bias stress at elevated temperatures. The DC device characteristics are monitored to evaluate the effect of bias/temperature stress on a large number of devices fabricated on MBE (molecular beam epitaxy) grown material. The primary degradation observed in some devices is a reduction in the current gain which appears to be due to an electric field-aided diffusion of interstitial Be from the base into the base-emitter graded region. Other devices with optimal epitaxial material show stable current gain after DC bias stress at high temperature. Ohmic contact degradation, with or without bias, is also observed at the emitter contact, resulting in an increased emitter series resistance. >

A new approach to optimizing the base profile for high-speed bipolar transistors

Abstract: It is shown using first-order analytical analysis and extensive device simulations that, for a given base resistance and peak base doping, a uniform base profile gives a higher cutoff frequency than a graded profile. This result is explained by the narrower base width that can be achieved with a uniform profile, which more than compensates for the lack of the aiding electric field present in graded-base transistors. >

SiGe-base heterojunction bipolar transistors: physics and design issues

Abstract: It has been shown that SiGe technology has the capability to extend the performance of Si bipolar transistors at both high and low current levels. The ability to tailor the bandgap, independently of the doping profile design, provides considerable flexibility for optimizing cutoff frequency, intrinsic base resistance, and junction capacitances for a given application. It is concluded that, when combined with a self-aligned process, SiGe can significantly improve the speed of Si bipolar circuits. >

Method of manufacturing super self-alignment technology bipolar transistor

Abstract: This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.

On the very-high-current degradations on Si n-p-n transistors

Abstract: The stressing of 0.8- mu m double-poly self-aligned Si n-p-n transistors at current densities up to 12.5 mA/ mu m/sup 2/ is discussed. The emitter contact does not fail abruptly; rather, its contact resistance drifts gradually. The contact resistance increases when the current flows out of the emitter and decreases when the current is reversed. The drift in emitter resistance can be thermally accelerated and is consistent with the electromigration phenomenon. The emitter-base junction shows negligible degradation when stressed in normal-mode operation, i.e. the current flows out of the emitter. However, the junction degrades when stressed with open collector or when stressed in inverse mode. The annealing experiments show that the junction degradation results from the interface-state generation. However, the drift in contact resistance cannot be recovered by annealing. The causes of junction degradation are suggested. >

Closed cell transistor with built-in voltage clamp

Abstract: A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.

50-GHz self-aligned silicon bipolar transistors with ion-implanted base profiles

Abstract: Silicon bipolar transistors having cutoff frequencies from 40 to 50 GHz have been fabricated in a double -polysilicon self-aligned structure using a process which relies on ion implantation for the intrinsic base formation. The devices have nearly ideal DC characteristics, with breakdown voltages adequate for most digital applications. The results demonstrate that the performance limits of conventional implanted technologies are significantly higher than previously thought. >